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NOEL-ARTYA7-EX-UM

Jul 2022, Version 2.0

10

NOEL-ARTYA7-EX

 

Cobham Gaisler AB

Kungsgatan | SE-411 19 | Goteborg | Sweden

+46 31 7758650 | www.caes.com/gaisler

4

Working with the board

4.1

Prerequisites

The following items are required to use NOEL-ARTYA7-EX designs:
•

Workstation with Windows or Linux

•

 Arty A7: Artix-7 FPGA Development Board (A7-100T version)

•

NOEL-ARTYA7 bitstream

•

GRMON3 debug monitor

The two last items can be downloaded via http://gaisler.com/NOEL-ARTYA7.
Cobham Gaislers standard offer of toolchains can be used to build and run software on the NOEL-

ARTYA7-EX designs. Toolchains and run-time environments are available for download via http://

gaisler.com.

4.2

Programming the FPGA device and connecting with GRMON3

Please see the NOEL-ARTYA7-EX Quick Start Guide [QSG] for information on FPGA programming

and using the SoC design.

4.3

Support

In case of technical issues please contact [email protected]. The support line is normally available

only  to  companies  and  institutions  with  active  support  contracts.  Limited  support  for  the  NOEL-

ARTYA7-EX example designs is provided. When contacting support please provide a clear descrip

-

tion of which design that is used and your affiliation.
Sales and licensing questions should be directed to [email protected].
There is also an open forum available at https://grlib.community .

Содержание RISC-V NOEL-ARTYA7-EX

Страница 1: ...ler RISC V standard PMP RISC V standard debug support Level 2 cache DDR4 SDRAM UART Timers GPIO port Status registers Ethernet 10 100 Mbit MAC interface Description The NOEL ARTYA7 FPGA bitstreams are...

Страница 2: ...2 Document revision history 3 1 3 Reference documents 3 2 Example designs 4 2 1 Overview 4 2 2 Configurations 5 3 Architecture 6 3 1 Cores 6 3 2 Interrupts 6 3 3 Memory map 6 3 4 IP core documentation...

Страница 3: ...n Hi Rel and Synopsys Synplify Premier This document describes ready made FPGA configurations bitstreams that have been built from a GRLIB template design More information about the NOEL V processor i...

Страница 4: ...Debug AHB bus The full NOEL ARTYA7 architecture includes the following modules NOEL V with 16 KiB instruction cache and 16 KiB data cache Debug Support Unit with UART Ethernet and JTAG Debug Links Le...

Страница 5: ...ftware may report that fault tolerance is enabled for the example designs the bit streams are not suitable for use in harsh environments Table 2 Example configurations Configuration name MC32L SC GP32...

Страница 6: ...designs use the same memory map for all standard configurations The memory map shown in table 5 is based on the AMBA AHB address space An access to addresses outside the Table 3 Used IP cores Core Fu...

Страница 7: ...FFFFFFF DDR4 SDRAM area AHBROM 0xC0000000 0xC001FFFF Registers CLINT 0xE0000000 0xE000FFFF Registers PLIC 0xF8000000 0xFBFFFFFF Registers GPTIMER 0xFC000000 0xFC0000FF Registers APBUART0 0xFC001000 0x...

Страница 8: ...isler NOEL ARTYA7 EX 3 4 IP core documentation This user manual does not contain IP core documentation Please refer to the GRLIB IP Core User s Manual GRIP available at http gaisler com products grlib...

Страница 9: ...teborg Sweden 46 31 7758650 www caes com gaisler 3 5 Signals Please see the NOEL ARTYA7 EX Quick Start Guide QSG for information on FPGA pinout 3 6 Resource utilization Resource utilization is describ...

Страница 10: ...EX designs Toolchains and run time environments are available for download via http gaisler com 4 2 Programming the FPGA device and connecting with GRMON3 Please see the NOEL ARTYA7 EX Quick Start Gui...

Страница 11: ...2022 Version 2 0 11 Cobham Gaisler AB Kungsgatan SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler NOEL ARTYA7 EX 5 Ordering information Please contact sales gaisler com for information on...

Страница 12: ...the application or use of any product or service described herein except as expressly agreed to in writing by Cobham nor does the purchase lease or use of a product or service from Cobham convey a lic...

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