DAMC-FMC20 User’s Manual
12
On HPC FMC, while the LPC pins (36 lanes) can operate in bidirectional mode,
the additional HPC pins (40 lanes) are input-only LVDS.
If outputs on these pins are desired, other standards such as LVCMOS25 must be
used.
2.1
Clock Tree
The DAMC-FMC20 has a flexible clock tree, since FPGA global clocks can be
accessed from PCIe clock as well as from TCLKA or TCLKB. Furthermore, local 200
MHz oscillators are present for booth FPGAs.
A clock from RTM is fed to the main FPGA and to the transceiver FPGA. A
multiplexer selects if TCLKA or TCLKB are output to RTM.
The clock tree diagram is presented below:
PLL
PCIe Clk
Buffer
PCIe Clk x 2.5
PCIe Clk x 2.5
PCIe Clk x 2.5
TCLKA
Buffer
TCLKB
TCLKA
TCLKA
TCLKB
TCLKB
TCLKA
XC6SLX150
XC6SLX45T
GC
GC
RTM
GC
RTM_CLK
GC
TCLKA or TCLKB
GC
TCLKA
TCLKA
TCLKB
RTM_CLK
TCLKB
GC
GC
From CPLD
(50 MHz div 1..16)
MUX
TCLKB
RTM Clocks
PCIe Clk x 2.5
PCIe Clk x 2.5
FMC
HPC
FMC
LPC
MGT101CLK
PCIe Clk x 2.5
GBTCLK0_M2C
GBTCLK0_M2C
RTM_CLK
125
MHz
LVDS
RTM/ 125MHz
MGT123CLK
GC
AMC_CLK
From CPLD
(50 MHz div 1..16)
The clock tree provides following features:
Distribution of PCI clock (multiplied by factor 2.5) to transceiver FPGA GTP
block, transceiver FPGA global clock and main FPGA global clock;
Distribution of TCLKA to transceiver FPGA global clock, main FPGA global
clock and RTM (multiplexed with TCLKB);
