Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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3.9 Prototyping Area
The RDK board contains a large prototyping area that contains 28 surface mount footprints, one 0.05”
pitch BGA landscape, a 25x25 0.1” grid through-hole prototyping area and 5 power rails.
Table 3-3. PCI 9052RDK-LITE Board Prototyping Area Footprints
Package Qty. Width & Pitch Destination Comments
32-pin PLCC 1 0.05” pitch FP1
Populated with
PLCC socket
84-pin PLCC 1 0.05” pitch FP2
68-pin PLCC 1 0.05” pitch FP3
44-pin PLCC 1 0.05” pitch FP4
28-pin PLCC 1 0.05” pitch FP5
FP2 to FP5
co-exist at an
84-pin PLCC
area
20-pin PLCC 1 0.05” pitch FP6
16-pin SOIC narrow 4 .150”wide, 0.05” pitch FP7, 8, 15, 16
54-pin TSOP 2 0.8mm pitch FP9, 10
48-pin SSOP 2 .300”wide, 0.025” pitch FP23, 24
20-pin SOIC wide 4 .300”wide, 0.05” pitch FP17, 18,19,20
24-pin SSOP 2 .150”wide, 0.025” pitch FP21, 22
44-pin TQFP 1 0.8mm pitch FP25
16-Pin SSOP 2 .150” wide, 0.025” pitch FP26, 27
208-pin PQFP 1 0.5mm pitch FP28
144-pin TQFP 1 0.5mm pitch FP29
80-pin TQFP 1 0.5mm pitch FP30
FP28, 29, 30
co-exist in a
208-pin PQFP
area
176-pin PQFP 1 0.5mm pitch FP31
100-pin TQFP 1 0.5mm pitch FP32
48-pin TQFP 1 0.5mm pitch FP33
FP31, 32,33
co-exist in a
176-pin PQFP
area
26x26 BGA matrix 1 0.05” pitch
25x25 0.1” through hole area
2 @ 1x30 0.1” through hole rails for 3.3VCC
2 @ 1x30 0.1” through hole rails for GND
1 @ 1x30 0.1” through hole rail for 5VCC
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved . 11