Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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3. RDK Hardware Architecture
3.1 Architecture Overview
A block diagram of the PCI 9052RDK-LITE board is shown in Figure 3-1. The board is designed to
support the product development of 32-bit, 33 MHz PCI target adapters. It features a PLX PCI 9052
device that interfaces user logic to a 32-bit, 33 MHz PCI bus. An on-board serial EEPROM contains the
data that is loaded into the PCI 9052 configuration registers during board boot-up. A socketed 32 MHz
oscillator drives the local bus side of the RDK. The local bus can be programmed to operate as an 8- or
16-bit ISA bus, or as an 8-, 16-, or 32-bit multiplexed or non-multiplexed address/data bus. A glue-less
ISA bus connector is provided on the board to facilitate the rapid conversion of ISA bus designs to PCI
bus designs. An unpopulated 512KB 8-bit wide ROM socket is provided for memory expansion. The
board supports continuous PCI 9052 burst read/write accesses to 128 Kbytes of SRAM provided in a 32-
bit wide format. An inexpensive 64-macrocell CPLD is used to generate various control signals for the
RDK board. While not required to interface the PCI 9052 to the ISA bus, using a small CPLD makes the
RDK as flexible as possible as a development platform. Additional logic capacity is available in the CPLD
for prototyping. The local bus is brought out to test headers to facilitate the debugging of user designs. A
large prototyping area is provided as well.
PCI 9052
PCI Bus
32-bit, 33MHz
Control
Data
Address
Serial
EEPROM
Clock Div.
by 1,2,4
select
Local Bus
Clock Circuit
32 MHz
Programmable
Logic Device (PLD)
EPM3064ATC100
PC1-21
User connections to
PLD with 15 spare
Clock / 2
Clock / 4
Prototyping
Area &
Footprints
SRAM/ROM CS
config jumpers
ISA
Interface
Connector
Address
Data
Control
ROM
Socket
SRAM
32K X 32
Test
Headers
Local Bus
32-bit, up to 40MHz
Figure 3-1. PCI 9052RDK-LITE Hardware Block Diagram
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved . 5