1
System and memory overview
1.1 Introduction
The on-chip processor uses RISC-V 32-bit with floating point. With high-speed processing memory system (see
the L1C chapter for details), to achieve high-quality computing efficiency. External to the processor is a multilayer
32-bit AHB architecture with low power consumption, low latency, and high flexibility. The memory section contains
high-speed tightly coupled memory as well as cache and system shared memory. Off-chip memory supports Flash
expansion.
1.2 Main features
• RISC-V 32-bit with floating point
• Multi-layer 32-bit AHB bus architecture
• 96KB high-speed memory
• 180KB system memory
• 128KB read-only memory
• Off-chip memory Flash
1.3 Function description
The BL602 bus connection and address access are summarized as follows: The bus master includes CPU, SDIO,
DMA, encryption engine, and debug interface. The bus includes memory, peripherals, WiFi / BLE. Except the en-
cryption engine can only access the memory, all other bus masters can access all bus slaves.
BL602/604 Reference Manual
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