BitFlow NEO-PCE-CLB, Справочник по аппаратуре

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Encoder Divider Encoder Divider Details
Version G.5 BitFlow, Inc. NEO-5-3
5.2.4 PLL Locking
The encoder divider achieves its scaling using a PLL. By default the output waveform
is locked to the input waveform. However, this locking can result in a small amount of
jitter. To reduce the jitter, the output waveform can be run open loop. This mode is
accessed by setting the register ENC_DIV_OPEN_LOOP to 1.
5.2.5 Handling Encoder Slow Down or Stopping
On some machine vision systems, the encoder is attached to a mechanism that may
slow and/or stop. Any PLL has a limited range that it can track (based on the PLL mas-
ter clock), outside of this range, the output signal can become unpredictable. The
Encoder Divider circuit’s master clock is 50 MHz, which makes the minimum fre-
quency that it can accurately track around 1.6 KHz. In order to avoid this situation and
handle encoder slow down/stop gracefully, the encoder divider has has limiting cir-
cuit that can be run in one of two different mode described in the following two sec-
tions.
Slow Tracking Mode (ENC_DIC_FORCE_DC = 0)
In this mode, when the input frequency goes below the minimum of 1.6 KHz, the
Encoder Divider circuit’s output will continue to track the input, but the output fre-
quency will become simple divider on the input freqency. In this mode the output will
track the input using the following formula (the variables are the same as in Section
5.2.1)
DC Mode (ENC_DIV_FORCE_DC = 1)
In this mode, the Fin goes below 1.6 KHz, Fout will goes to DC. This means that when
the input frequency goes below the minium, the camera will be frozen, acquisition
will stop. The board will stay in this state until Fin goes above 1.6 KHz. This is useful
when the encoder is being driven by a stage that is travelling back and forth. At both
ends of travel when the stage changes directions, the board will not acquire.
F
out
F
in
4M
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