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Plexus 9000 Planning and Engineering Guide
Front Dual System Processor Timing Module 3
Section 130-120-220
Issue 1, April 23, 2004
Telica, Inc.
5-59
SP/TMG Module
I/O Module
P454-AA
03-18-02
FRAMER 1
FRAMER 2
FRAMER 3
FRAMER 4
BITS-Primary
BITS - Secondary
TEST Port Busses
in Midplane
EN-TST-PRT
TST-RDO
J7 - SP Rear
J8 - SP Rear
J10 - SP Rear
Monitor
Function
MLBA-TM
TSU
TST-XDI
MON-XDI
To Other
Cards
T-EN-MON-PRTX
F-EN-TST-PRTX
FSU
Figure 5.4-3. Monitor Jacks and the Front System Processor
5.4.3.3 Ethernet
Switch
This circuitry provides all Ethernet access to and from the master and
slave processors allowing either processor connection to any of the
Ethernet ports. Connections to the switch include the ENET port on the
front of the module and the SIG A, SIG B, SIG C, SIG D and OS ports on
the rear module. Shown on the diagram are two connections labeled SS7
that connect to the SS7 processors on the rear modules when using the 89-
407 rear SP3s. The front Ethernet port of the SP3 is further described in
the
paragraph.
5.4.3.4 Processor
Section
The processor section includes two on-board microprocessors with
memory. It provides the Ethernet interface for the front and rear modules,
the USB interface for the rear module and the serial RS-232 interface on
the front and rear modules. It also contains an IDE controller for the disk
drive located on the rear SP3 module and a PCI bridge to the SF module.