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Technical
Reference
61
interconnection
between
the
two
DMA
devices,
thereby
maintaining
IBM
PC/AT
compatibility.
The
following
is
the
system
information
of
DMA
channels:
DMA
Controller
1
DMA
Controller
2
Channel
0:
Spare
Channel
4:
Cascade
for
controller
1
Channel
1:
Reserved
for
IBM
SDLC
Channel
5:
Spare
Channel
2:
Diskette
adapter
Channel
6:
Spare
Channel
3:
Spare
Channel
7:
Spare
6
6
Serial
Ports
The
ACEs
(Asynchronous
Communication
Elements
ACE1
to
ACE2)
are
used
to
convert
parallel
data
to
a
serial
format
on
the
transmit
side
and
convert
serial
data
to
parallel
on
the
receiver
side.
The
serial
format,
in
order
of
transmission
and
reception,
is
a
start
bit,
followed
by
five
to
eight
data
bits,
a
parity
bit
(if
programmed)
and
one,
one
and
half
(five
‐
bit
format
only)
or
two
stop
bits.
The
ACEs
are
capable
of
handling
divisors
of
1
to
65535,
and
produce
a
16x
clock
for
driving
the
internal
transmitter
logic.
Provisions
are
also
included
to
use
this
16x
clock
to
drive
the
receiver
logic,
also
included
in
the
ACE
a
completed
MODEM
control
capability,
and
a
processor
interrupt
system
that
may
be
software
tailored
to
the
computing
time
required
to
handle
the
communications
link.
The
following
table
is
a
summary
of
each
ACE
accessible
register
DLAB
Port
Address
Register
0
Base
+
0
Receiver
buffer
(read)
Transmitter
holding
register
(write)
0
Base
+
1
Interrupt
enable
X
Base
+
2
Interrupt
identification
(read
only)
