© BECOM Systems 2020
Hardware User Manual - CM-BF527
Last change: 26. March 2019/Version 7
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4
Connector Description
In the following tables you will find pin assignments for the Core Module connectors. Most pins are directly
connected to the Blackfin processor. If not, please read the Notes below the table.
4.1
Connector X1
Pin No. Signal Name
Type
Function
1
VppOTP
Power
1)
OTP programming voltage
2
PH11/ND_WE/ETxD3/HOST_D11
IO
NAND Interface
3
PH13/ND_BUSY/ERxCLK/HOST_D13
IO
NAND Interface
4
PH15/ND_ALE/COL/HOST_D15
IO
NAND Interface
5
CLKBUF
IO
Buffered clock (50MHz)
6
SDA
IO
I2C
7
PG9 / RSCLK0A/ TMR5 / TACI5
IO
SPORT, Timer
8
NC
2)
or PG11 / TMR7 / HOST_WR
IO
–
10k pull down Timer
9
Vin 3V3
Power
10
Vin 3V3
Power
11
PF0 / PPID0 / DR0PRI / ND_D0A
IO
PPI data, SPORT, NAND
interface
12
PF2 / PPI D2 / RSCLK0 / ND_D2A
IO
PPI data, SPORT, NAND
interface
13
PF4 / PPI D4 / TFS0 / ND_D4A / TACLK0
IO
PPI data, SPORT, NAND
interface
14
PF6 / PPI D6 / DT0SEC / ND_D6A / TACI0
IO
PPI data, SPORT, NAND
interface
15
PF8 / PPID8 / DR1PRI
IO
PPI data, SPORT
16
PF10 / PPID10 / RFS1 / SPISEL7
IO
PPI data, SPORT
17
PF12 / PPID12 / DT1PRI / SPISEL2 / CDG
IO
PPI data, SPORT
18
PF14 / PPID14 / DT1SEC / UART1TX
IO
PPI data, SPORT, UART
19
PG6 / DT0PRIA / TMR2 / PPIFS3
IO
SPORT, Timer, PPI frame sync
20
PPIFS1 / TMR0
IO
PPI frame sync, Timer
21
PPIFS1 / TMR0
IO
PPI frame sync, Timer
22
PG13 / DMAR0 / UART1RXA / H_ADR / TACI2
IO
UART
23
PG8 / TMR4 / RFS0A / UART0RX / TACI4
IO
Timer, SPORT, UART
24
PG4 / SPIMOSI / DT0SECA
IO
SPI, SPORT
25
PG2 / SPISCK
IO
SPI clock
26
Bmode0
I - 10k pull down
Boot mode
27
GND
Power
28
TCK
I - 10k pull up
JTAG
29
TDI
I - 10k pull up
JTAG
Содержание CM-BF527
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