Chapter:
BIOS Settings
Chipset
page 66
Beckhoff New Automation Technology
CB4055
5.4.1.1
PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration │Enable or disable PCI Express │
│ │Clock Gating for each root │
│ PCI Express Clock Gating [Enabled] │port. │
│ DMI Link ASPM Control [Enabled] │ │
│ DMI Link Extended Synch Control [Disabled] │ │
│ PCIe-USB Glitch W/A [Disabled] │ │
│ Subtractive Decode [Disabled] │ │
│ │ │
│ PCI Express Root Port 1 │ │
│► PCI Express Root Port 2 │ │
│► PCI Express Root Port 3 │ │
│► PCI Express Root Port 4 │ │
│ PCIE Port 5 is assigned to LAN │────────────────────────────────│
│ PCIE Port 6 is assigned to LAN2 │→←: Select Screen │
│ PCIE Port 7 is assigned to PCIe to PCI Bridge │↑↓: Select Item │
│► PCI Express Root Port 8 │Enter: Select │
│ │+/-: Change Opt. │
│ │F1: General Help │
│ │F2: Previous Values │
│ │F3: Optimized Defaults │
│ │F4: Save & Exit │
│ │ESC: Exit │
│ │ │
│ │ │
│ │ │
│ │ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.
PCI Express Clock Gating
Options:
Disabled / Enabled
DMI Link ASPM Control
Options:
Disabled / Enabled
DMI Link Extended Synch Control
Options:
Disabled / Enabled
PCIe-USB Glitch W/A
Options:
Disabled / Enabled
Subtractive Decode
Options:
Disabled
PCI Express Root Port X
Sub menu: see "PCI Express Settings" (page 67)
