
REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 74 of 163
7.13.2
USB OTG Design
Figure 34
is the design of the USB OTG port on the BeagleBoard.
P1
mini USB-AB
D-
2
D+
3
VB
1
ID
4
G2
7
G3
6
G1
5
G5
8
G4
9
+
J1
JMP
1
2
U7A
TPS65950
VBUS
R8
DP
T10
DN
T11
ID
R11
UCLK
L15
STP
L14
DIR
L13
NXT
M13
DATA0
K14
DATA1
K13
DATA2
J14
DATA3
J13
DATA7
F13
DATA6
F14
DATA4
G14
DATA5
G13
USB_CLIENT /
OTG PORT
D1
PGB0010603MR
D2
PGB0010603MR
D3
PGB0010603MR
D4
PGB0010603MR
VBUS_5V0
USB0HS_DAT2
4
USB0HS_CLK
4
USB0HS_DAT1
4
USB0HS_DAT5
4
USB0HS_DAT0
4
USB0HS_DAT6
4
USB0HS_DIR
4
USB0HS_DAT4
4
USB0HS_STP
4
USB0HS_DAT7
4
USB0HS_NXT
4
USB0HS_DAT3
4
R57
0,0603
VBUS_5V0
C
864.7uF,6.3V,0603
C3
0.1uF,10V
Figure 35.
USB OTG Design
7.13.3
OTG ULPI Interface
ULPI is an interface standard for high-speed USB 2.0 systems. It defines an interface
between USB link controller (processor) and the
TPS6595
0 that drives the actual bus.
ULPI stands for UTMI+ low pin interface and is designed specifically to reduce the pin
count of discrete high-speed USB PHYs. Pin count reductions minimize the cost and
footprint of the PHY chip on the PCB and reduce the number of pins dedicated to USB
for the link controller.
.
Unlike full- and low-speed USB systems, which utilize serial interfaces, high-speed
requires a parallel interface between the controller and PHY in order to run the bus at
480Mbps. This leads to a corresponding increase in complexity and pin count. The ULPI
used on the BeagleBoard keeps this down to only 12 signals because it combines just
three control signals, plus clock, with an 8-bit bi-directional data bus. This bus is also
used for the USB packet transmission and for accessing register data in the ULPI PHY.
7.13.3.1
Processor Interface
The controller for the ULPI interface is the Processor. It provides all of the required
signals to drive the interface.
Table 7
describes the signals from the processor that are
used for the USB OTG interface.
Содержание XM C2
Страница 33: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 33 of 163 Figure 5 USB OTG Connection ...
Страница 152: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 152 of 163 ...
Страница 153: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 153 of 163 ...
Страница 154: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 154 of 163 ...
Страница 155: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 155 of 163 ...
Страница 156: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 156 of 163 ...
Страница 157: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 157 of 163 ...
Страница 158: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 158 of 163 ...
Страница 159: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 159 of 163 ...
Страница 160: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 160 of 163 ...
Страница 161: ...REF BB_SRM_xM BeagleBoard xM System Reference Manual Revision C2 Page 161 of 163 ...