BeagleBoard XM C2, Справочное руководство

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REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 67 of 163
BeagleBoard processor, these pins provided access to the SDRAM bus. However, in the
case of the processor on the BeagleBoard–xM, these there are no signals on these pins.
7.10.3 GPMC Bus
The GPMC bus is not accessible on the BeagleBoard. Its connectivity is limited to the
POP memory access on the top of the processor and therefore is only accessible by the
NAND memory.
The memory on the GPMC bus is NAND and therefore will support the classical NAND
interface. The address of the memory space is programmable.
7.10.4 DSS Bus
The display subsystem provides the logic to display a video frame from the memory
frame buffer in SDRAM onto a liquid-crystal display (LCD) display via the DVI-D
interface or to a standalone LCD panel via the LCD interface connectors. The logic levels
of the LCD expansion connectors are 1.8V so it will require buffering of the signals to
drive most LCD panels. The DSS is configured to a maximum of 24 bits, but can be used
in lower bit modes if needed.
7.10.5 McBSP2
The multi-channel buffered serial port (McBSP) McBSP2 provides a full-duplex direct
serial interface between the processor and the audio CODEC in the
TPS65950 using the
I2S format. Only four signals are supported on the McBSP2 port. Figure 30 is a
depiction of McBSP2.
Figure 30. McBSP2 Interface
7.10.6 McBSP1
Processor