BeagleBoard BeagleBone AI-64, Справочное руководство системы, Страница: 32 / 45

MCU Domain
FSS
DDRSS
NAVSS
SERDES mux per IF
MSMC
8MB SRAM with ECC
PC
IE
0
(G
en
3
.0
)
A72SS
1MB L2
2 Arm ×
Cortex-A72
SERDES0
(2L)
U
SB
1
(U
SB
3.
0
D
ua
lR
ol
e)
U
SB
0
(U
SB
3.
0
D
ua
lR
ol
e)
In
te
rn
al
13 DCC ×
ESM
DebugSS
20 PLL ×
20 Timer ×
CTRL_MMR
10 WWDT ×
PC
IE
1
(G
en
3
.0
)
RINGACC
Proxy
Spinlock
eD
P/
D
P
D
PI
/B
T.
65
6/
BT
.1
12
0
PSI-L
2 TIMER_MGR ×
32b+in-line ECC
MCRC UDMA-P
CPTS
3 INTA ×
2 MCU_ADC ×
(12b/4MSPS)
2 MCU_CAN-FD ×
3 MCU_MCSPI ×
MCU_UART
2 MCU_I2C ×
QSPI
1024KB L3 RAM
10 Timers ×
3 MCU_PLL ×
2 MCU_WWDT ×
MCU_CTRL_MMR
MCU Internal Diagnostics
3x MCU_DCC
R5FSS
R5F R5F
D
ua
l/
Lo
ck
St
ep
I-cache 16KB
TCM 64KB
D-cache 16KB
I-cache 16KB
TCM 64KB
D-cache 16KB
Scra chpad RAM 512B t
12
M
C
AS
P
×
8
M
C
SP
I
×
8
G
PI
O
×
G
PM
C
/E
LM
10
U
AR
T
×
7
I2
C
×
M
M
C
SD
0
- 8
-b
it
14
M
C
AN
×
6
EP
W
M
×
3
eQ
EP
×
DMSC
ROM 160K
M3
WKUP_PLLCTRL
WKUP_PSC
2 WKUP_GPIO ×
WKUP_UART
WKUP_I2C
WKUP Domain
WKUP_CTRL_MMR
WKUP_ESM
R
eg
io
n
ba
se
d
FW
G
IC
50
0
PS
C
PL
LC
TR
L
PD
M
A
G
TC
MCU_CPSW
PSI-L
UDMA-P
Proxy MCRC
To NAVSS
To MCU NAVSS
M
M
C
SD
1/
2
- 4
-b
it
MCU_PDMA
GPU 8XE GE8430
INTA
C SS 71
512KB L2
1 × C71x
DSP+MMA
D
SS
1
C
SI
2
4L
TX
×
M
IP
I
-
2
C
SI
2
4L
R
X
×
M
IP
I
-
MAIN Domain
MCU_ESM
MCU NAVSS
SERDES1
(2L)
WKUP_VTM
Mailbox
DRU
W
KU
P
In
te
rc
on
ne
ct
M
C
U
In
te
rc
on
ne
ct
Local Interconnect
Lo
ca
l I
nt
er
co
nn
ec
t
RINGACC INTA
INTR
Channelized FW
Channelized FW
AES
SECMGR
Interconnect
C66SS
32KB SRAM +
max 256KB L2
2 C66x ×
DSP
2 R5FSS ×
TCM 64KB
Cortex-R5F
C
LE
C
I3
C
C
PS
W
(9
-p
or
t s
w
itc
h)
U
FS
3
eC
AP
×
AT
L
VP
FE
2 I3C ×
SERDES2
(2L)
SERDES3
(2L)
SERDES4
(4L)
SERDES
mux per IF
3 PVU ×
VIRTSS
5 PAT ×
SMMU
To VPAC
To DMPAC
To CSI
To CPSW
PC
IE
2
(G
en
3
.0
)
PC
IE
3
(G
en
3
.0
)
M
IP
ID
SI
D PHY -
(4L)
D PHY -
(4L)
D PHY RX -
H 264 Encoder .
VXE384MP2
H 264/5 Decoder .
D5520MP2
VP
AC
D
M
PA
C
MCU_ _ SA2 UL
D
ia
gn
os
tic
s
MIPI
D PHY TX -
MIPI
1 OSPI or ×
1 HBMC ×
D PHY -
(4L)
2
M
IP
I
×
512KB SRAM
SA2 UL _
4 Arm ×
Figure 19. Device Top-level Block Diagram
5.2. Memory
Described in the following sections are the three memory devices found on the board.
5.2.1. 4GB LPDDR4
A single (1024M x 16bits x 2channels) LPDDR4 4Gb memory device is used. The memory used is is:
• Kingston Q3222PM1WDGTK-U
5.2.2. 4Kb EEPROM
A single 4Kb EEPROM (24FC04HT-I/OT) is provided on I2C0 that holds the board information. This
information includes board name, serial number, and revision information.
5.2.3. 16GB Embedded MMC
A single 16GB embedded MMC (eMMC) device is on the board. The device connects to the MMC1
port of the processor, allowing for 8bit wide access. Default boot mode for the board will be MMC1
with an option to change it to MMC0, the SD card slot, for booting from the SD card as a result of
removing and reapplying the power to the board. Simply pressing the reset button will not change
30