BeagleBoard BeagleBone AI-64, Справочное руководство системы, Страница: 31 / 45

• DDR Subsystem (DDRSS) with Error Correcting Code (ECC), supporting LPDDR4
• 1KB RAM with ECC support for C71x boot vectors
• 2KB RAM with ECC support for A72 and R5F boot vectors
• 512KB On-Chip SRAM protected by ECC
• One Global Time Counter (GTC) module
• Thirty 32-bit counter timers with compare and capture modes
• Debug and trace capabilities
The device includes different modules for functional safety requirements support:
• MCU island with dual lock step Arm Cortex-R5F
• Safety enabled interconnect with implemented features to help with Freedom From
Interference (FFI)
• Twelve Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)
functionality to monitor processor cores
• Sixteen Dual-Clock Comparators (DCC) to monitor clocking sources during run-time
• Three Error Signaling Modules (ESM) to enable error monitoring
• Temperature monitoring sensors
• ECC on all critical memories
• Dedicated hardware Memory Cyclic Redundancy Check (MCRC) blocks
The device supports the following main security functionalities among others:
• Secure Boot Management
• Public Key Accelerator (PKA) for large vector math operation
• Cryptographic acceleration (AES, 3DES, MD5, SHA1, SHA2-224, 256, 512 operation)
• Trusted Execution Environment (TEE)
• Secure storage support
• On-the-fly encryption and authentication support for OSPI interface
The device is partitioned into three functional domains as shown in Device Top-level Block
Diagram , each containing specific processing cores and peripherals:
• Wake-up (WKUP) domain
• Microcontroller (MCU) domain with one of the dual Cortex-R5 cluster
• MAIN domain
29