Bayer HealthCare RapidPoint 400 Series, Руководство по обслуживанию, Страница: 92 / 458

92 Rev. C
UIP Main Interconnect Board ISA Interface
Digital Input Signals
Digital Output Signals
Input Signal Description
+12_VDC +12 VDC from the power supply.
-12_VDC -12 VDC from the power supply.
+5_VDC +5 VDC from the power supply.
GND Ground return for the +5 VDC to the power supply.
DRQ0-DRQ3
DRQ5-DRQ7 DMA requests. These signals are asynchronous channel
requests used by peripheral devices and a microprocessor to
gain DMA service or control of the system.
I/OCHCK I/O channel check. This signal provides the system board
with parity (error) information about memory or devices on
the I/O channel.
I/OCHRDY I/O channel ready. A memory or I/O device pulls this signal
low to lengthen I/O or memory cycles.
I/OCS16- I/O 16-bit chip select.
IRQ3-IRQ7
IRQ9-IRQ12
IRQ 14, IRQ15 Interrupt request lines. These lines signal the
microprocessor when an I/O device requires attention. An
interrupt request is generated when an IRQ line is raised
from low to high. The line is high until the microprocessor
acknowledges the interrupt request.
Master- Signal used with DRQ to gain system control.
MEMCS16- Memory 16-bit chip select.
0WS Zero wait-state. This signal directs the microprocessor to
complete the present bus cycle without inserting any
additional wait cycles.
Output Signal Description
AEN Address enable. This signal disconnects the microprocessor
and other devices from the I/O channel and enables DMA
transfers.
BALE Buffered address latch enable. This signal originates from
the bus controller and is used on the system board to latch
valid addresses and memory decodes from the
microprocessor.
(Continued)