Bayer HealthCare RapidPoint 400 Series, Руководство по обслуживанию, Страница: 84 / 458

84 Rev. C
The address bus, named AM1 to AM19, is passed to the memory section
and then to address latches inside U11. These latch a valid address on the
falling edge of signal AS-. The address signals to these latches are pulled
up by RN28, R235, R236, R237, and R238 to form the address bus A1 to
A15. This address bus is then sent to address decoder CPLD U37.
DEBUG/XRAY connector J30 is an expansion connector that connects the
main board to a diagnostic board.
RTP EPROM and PSRAM Circuitry
This section of the Main board contains the code memory EPROM and
data memory PSRAM devices U57, U48, U56, and U41.
The data in the PSRAMs is volatile and is refreshed periodically by the
68332 TPU section.
RTP Address Bus Decoder and Memory Controller Complex
Programmable Logic Device Circuitry
This section of the Main board contains a group of circuits located in the
single complex programmable logic device (CPLD), U37. The majority of
this IC takes the address bus signals A1 to A15, chip select signals CS9 to
CS10 and other 68332 control signals, such as R/W, and forms various
strobe signals that latch data in and out of U38.
Another function of U37 is to provide clock signal ADS_2 MHz for use by
the main A/D converter. This clock is enabled only when the A/D converter
busy signal is active.
U37 also arbitrates when a memory refresh cycle is needed by the
PSRAMs U56 and U41 by responding to a refresh request from the 68332
TPU unit on pin 147 of U37. It responds by delaying the start of a normal
memory request by inhibiting the pin 150 (DSACK1) signal. This delay
causes the 68332 to insert wait states until the refresh cycle is completed.
The IC also enables and buffers all of the interrupt signals coming from the
FIFO, A/D, debug and power-fail circuits. All outputs and the internal timing
of U37 are synchronized to the 68332 master clock (RCLK1) on pin 139. All
outputs on U37 become tri-state by pulling pin 140 to a high signal level.