AZZA U694 Series, Руководство пользователя

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The
AZZA
U694 MAINBOARD SERIES
Page 33
OnChip IDE Channel 0/1
The chipset contains a PCI IDE interface with support for two IDE channels. Select En-
abled to activate the primary IDE interface. Select Disabled to deactivate this interface.
IDE Prefetch Mode
The onboard IDE drive interfaces supports IDE prefetching for faster drive accesses. If
you install a primary and/or secondary add-in IDE interface, set this field to Disabled if the
interface does not support prefetching.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable transactions
then burst on the PCI bus and nonburstable transactions don’t.
PCI Master 0 WS Write
When
Enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
PCI#2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes (difault). When en-
abled, PCI#2 will be disconnected if max retries are attempted without success.
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are executed with one wait
states.
AGP Master 1 WS Read
When
Enabled, read to the AGP (Accelerated Graphics Port) are executed with one wait
states.
Memory Parity/ ECC Check
This item enabled to detect the memory parity and Error Checking & Correcting.
Managing The PC BIOS
3.6. Integrated Peripherals
(The menu is on page 34)