The
AZZA
U601 Mainboard Series
Page 32
DRAM Clock
DRAM Timing By SPD
SDRAM Cycle Length
Bank Interleave
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
AGP Aperture Size
OnChip USB
USB Keyboard Support
OnChip Sound
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI #2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
:By Auto
:Disabled
:3
:Disabled
:Disabled
:Enabled
:Enabled
:Disabled
:Disabled
:8M
:64M
:Enabled
:Disabled
:Enabled
:Enabled
:Enabled
:Enabled
:Enabled
:Disabled
:Disabled
:Disabled
Item Help
Menu Level
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CMOS Setup Utility - Copyright (C) 1984 - 2001 Award Software
Advanced Chipset Features
3.5. Advanced Chipset Features
DRAM Clock
This field allows you to select the DRAM access speed control to the memory
performance.
DRAM Timing By SPD
When you select enabled, the system BIOS will read the DRAM parameters
from the SPD chip on the DIMM module and set the DRAM timing automati-
cally.
SDRAM Cycle Length
Before SDRAM can execute a read command that it receives, there is a delay
time, which is measured in clock cycles (CLK). The lower the delay time the
faster the execution of commands will be. It is therefore desirable to minimize
this cycle length. Some memory modules are unable to deal with short delay
times. We recommend that you set this delay time between 2 and 3 CLK’s (the
default is 3). If your system becomes unstable we recommend that you in-
crease the delay time.
Managing the PC BIOS
