VIA 82C694 ATX Mainboard
AWARD BIOS SETUP
4-8
DRAM Timing By SPD
When enabled, the system BIOS will read the DRAM parameters from the SPD
chip on the DIMM module and set the DRAM timing automatically.
DRAM Clock
This field allows you to select the DRAM access speed to control the memory
performance.
DRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified unless you have the technical background.
BANK Interleave
This field allows you to select how many bank of DRAM is installed on the
mainboard so that the system BIOS will be able to adjust the SDRAM interleave
access mode to optimize the SDRAM performance.
Memory Hole
In order to improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below 16MB. This
field allows you to decide the memory mapping.
P2C/C2P Concurrency
This selection field allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency.
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Video RAM Cacheable
Select Enabled allows caching of the video RAM , resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
