Avnet PicoZed FMC V2 Скачать руководство пользователя страница 31 | Manualshive

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22 Sept 2016

v1.1

2.19 Fan Header – JP3

JP3, a three pin 0.85” pitch fan header has been placed to allow the customer to use a fan for
SOM cooling if needed. By default the header is connected to the VIN_SW which is +12V via
R161. If a 5V fan is desired, remove R161 and populate R162 with a 0402 zero ohm resistor.

Figure 19 – Fan Header connections

2.20 JTAG Configuration – J7

An auto switching JTAG interface port is provided on the PZCC-FMC-V2 through J7, a PC4
compliant connection. The port defaults to SOM JTAG operation unless an FMC board is
placed. Upon insertion of a FMC board, the interface will switch the FMC into the JTAG chain
via U3.

A Xilinx JTAG platform cable (HW-USB-II-G) or a Digilent JTAG HS2 or HS3 programming
cable should be used when programming via these ports. Diode D18 on the VREF pin is used
to prevent the JTAG cable from back feeding into the PZCC-FMC-V2 3.3V power supply.

Pullup resistors R191, R192, R193 are not populated by default as the FMC module should
have the pullup resistors in place. However, if the FMC module does not have the pullups, this
resistor pack can be placed.

Figure 20 – SOM & FMC JTAG Topology

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Содержание PicoZed FMC V2

Страница 1: ...1 22 Sept 2016 v1 1 PicoZed FMC Carrier Card V2 PZCC FMC V2 Revision 1 1 Hardware User Guide Version 1 1 ...

Страница 2: ...hernet RJ45 J9 25 2 14 MAC ID EEPROM 26 2 15 MAC ID UNI O EEPROM 7Z015 30 only 27 2 16 Real Time Clock Maxim DS3231MZ 27 2 17 HDMI Interface J10 29 2 18 microSD Card Interface 30 2 19 Fan Header JP3 31 2 20 JTAG Configuration J7 31 3 Power 32 3 1 Power Input J2 SW7 32 3 2 Molex to Non ATX connection 33 3 3 Power Rails 33 3 4 2 5V LDO U12 33 3 5 JP1 FPGA VBAT VCCBATT 34 3 6 VADJ selection JP5 34 3 ...

Страница 3: ...available on the PS PL Programmable Logic POR Power On Reset PS Processing System SMPS Switch Mode Power Supply SOM System On Module SoC System On Chip Xilinx Zynq 7000 Pmod Peripheral Module FMC FPGA Mezzanine Card LPC Low Pin Count Table 1 Glossary of Acronyms 1 2 Additional Documentation Specific Zynq pin connections are not called out in this document These are available in either the PicoZed ...

Страница 4: ...J45 Ethernet connector connected to PicoZed SOM PHY o Transceivers for 7015 30 SFP Interface PCIe x1 Gen 2 SMA FMC LPC o I2C SW programmable clock synthesizer with I2C configuration EEPROM o I2C Synthesizer Test Header spaced at 0 100 o USB UART Micro USB connector transceiver o USB 2 0 OTG USB Type A connector on the faceplate o MAC ID I2C EEPROM o MAC ID UNI O single wire EEPROM SFP MAC ID 7015 ...

Страница 5: ...upply 5V 4 Amp capable ADP5052 five channel SMPS IC VADJ 1 8V 2 5V 3 3V up to 4A user selectable voltage 3 3V VCCO_13 up to 4 0A 1 0V_AVCC up to 1 2 A 1 2V_AVTT up to 1 2 A 1 8V LDO 200mA o Wall Adapter Primary 12V 5 0A 2x3 connector NOTE not an ATX compatible power supply Figure 1 PZCC FMC V2 Block Diagram ...

Страница 6: ...6 22 Sept 2016 v1 1 Figure 2 PZCC FMC V2 Functional Block Diagram ...

Страница 7: ...7 22 Sept 2016 v1 1 Figure 3 PZCC FMC V2 Component Overview ...

Страница 8: ... both the carrier and SOM power supplies are within their regulation tolerance parameters and functional The signal is held low until the power supplies have completed their successful sequencing routine Green LED D4 illuminates when this signal is high The user can force this pin low by depressing SW9 which will trigger a reboot of the Zynq device Depressing this button will not cause a hard powe...

Страница 9: ...e When depressed the button provides a logic high on the respective net The switches are placed in a North South East West and Center position This is to allow the customer to better distinguish which button to press Below figure shows the locations of the user switches and the associated labeling These switches are located in the upper left corner of the PZCC FMC V2 board Figure 4 Push Button Ori...

Страница 10: ...green and blue are available to all other SOMs A logic high from the Zynq 7000 AP SoC I O turns the LED on LED s are sourced from the PZCC FMC V2 s 3 3V rail MIO Number Carrier Net Name JX MicroHeader Connection N A PL_LED1 JX1 17 N A PL_LED2 JX2 97 N A PL_LED3 JX2 99 N A PL_LED4 JX2 93 MIO47 PS_LED1 JX3 40 MIO50 PS_LED2 JX3 66 Table 5 User LED Connections ...

Страница 11: ... 0 0 R W HDMI Slave Addresses 0x72 Main Map slave address 0 1 1 1 0 0 1 R W 0x70 Packet Memory Map slave address controlled by Main Map Register 0x45 0 1 1 1 0 0 0 R W 0x78 CEC Map slave address controlled by Main Map Register 0xE1 0 1 1 1 1 0 0 R W 0x7C Fixed I2C Map slave address controlled by Main Map Register 0xF9 0 1 1 1 1 0 1 R W 0x7E CEC Map slave address controlled by Main Map Register 0xE...

Страница 12: ...puts 38 888MHz FMC_GBTCLK or PCIe_CLK The choice of how U13 handles the input and output clocks is configured in U14 1 Channel Q3 output Single ended output from 1 MHz to 200 MHz on SOM Bank 13 MRCC pin PL_CLK JX3 73 2 Channel Q3 INV output tied to test pad TP31 3 Channel Q2 output is a differential output derived from either the FMC clock or the PCIe clock and drives the SOMs MGT1 bank The choice...

Страница 13: ...ort design 13076 106 For more information on the Timing Commander tool http www idt com products clocks timing timing commander software download resource guide 2 5 PCIe x1 Gen2 Interface Note The PCIe data interface is available when using a PicoZed 7015 or 7030 SOM The PCIe x1 interface is not required for normal operation However it has been provided to assist in the development of PCIe based S...

Страница 14: ...igure 7 FMC Connections for topology overview When and FMC board is plugged in the FMC_PRSNT_N and FMC_PRSNT_VADJ_N signals are driven low per the FMC specification The FMC_PRSNT_N signal is used to switch the JTAG signals so the FMC card can be accessed through the JTAG interface When a FMC card is not present FMC_PRSNT_N is pulled high via R104 and the JTAG interface is isolated to the SOM only ...

Страница 15: ... bank 34 7010 20 Bank 35 7015 30 LA Bus 17 33 located in bank 35 7010 20 Bank 34 7015 30 CC Pairs 0 17 on MRCC pins CC Pairs 1 18 on SRCC pins To conserve SoC pins GA 1 0 pins are connected to header J9 see Section 4 1 for address selection Layout Routing Guidelines The signals for each header follow FMC routing tolerances and guidelines Each of the P N pairs have 50Ω single ended impedance 100Ω d...

Страница 16: ...3 _ P N VADJ VREF_A_M2C JX2 VCCIO VADJ LA17_ P N _CC LA18_ P N _CC CLK0_M2C_ P N LA00_ P N _CC LA01_ P N _CC CLK1_M2C_ P N Not Connected Not Connected Not Connected Not Connected MRCC SRCC MRCC MRCC SRCC FPGA Diff IO FPGA SE IO FPGA SE IO Not Connected TDI TDI TDO TDO U2 FPGA FMC_PRSNT_N Figure 7 FMC Connections Note The FMC slot SDA SCL and FMC_PRSNT signals are 3 3V levels For this reason level ...

Страница 17: ...ble or disable the SFP transmit laser When the jumper is placed the laser is enabled When the jumper is removed the laser is disabled unless a low is written to JSFP1 Pin 2 D13 is the LOS Loss Of Signal indicator It is silkscreened as LINK on the board This yellow LED will illuminate when a valid SFP link is established and maintained It will extinguish if there is not a link NOTE The PS_PMOD inte...

Страница 18: ...MMC interface please see the SOM s User Guide http picozed org support documentation 4736 JA Pmod SOM Net Name Carrier Net Name JX1 Connection JA PMOD Pin Number JA BANK13_LVDS_0_P JA0 1_P 87 1 BANK13_LVDS_0_N JA0 1_N 89 2 BANK13_LVDS_1_P JA2 3_P 88 3 BANK13_LVDS_1_N JA2 3_N 90 4 BANK13_LVDS_2_P JA4 5_P 91 7 BANK13_LVDS_2_N JA4 5_N 93 8 BANK13_LVDS_3_P JA6 7_P 92 9 BANK13_LVDS_3_N JA6 7_N 94 10 JB...

Страница 19: ...0 Position Dual Row BTB Vertical plugs These have variable stack heights from 5mm to 16mm making it easy to connect to a variety of carrier or system boards Each pin can carry 500mA of current The 5mm stack height is used on the PZCC FMC V2 and PicoZed SOMs support I O speeds up to 8 Gbps as shown in the following FCI customer presentation BergStak 0 8mm Mezzanine Connectors Customer Presentation ...

Страница 20: ...4 PL_LED x3 Zynq Bank 13 7 JTAG TMS_0 Zynq Bank 0 4 PS PS MIO PMOD eMMC x8 PG_MODULE Zynq Bank 500 9 TDI_0 Zynq Bank 0 TCK_0 Zynq Bank 0 CTRL VCCIO_EN Module Carrier 1 No Connect No Connect 1 TDO_0 Zynq Bank 0 PWR VADJ_34 35 Carrier 3 VADJ_13 Carrier 1 VIN_HDR Carrier 5 GND Carrier 23 CTRL FPGA_DONE Zynq Bank 0 1 Total 100 Carrier_SRST Carrier Drives bank 501 1 PWR_Enable Carrier 1 Power VIN_HDR C...

Страница 21: ... Bank 112 MGTREFCLK I Os Zynq Bank 112 PS SD_CARD Zynq Bank 501 7 USB_UART Zynq Bank 501 2 PS_PB1 PS_LED1 PS_LED2 Zynq Bank 501 3 SOM Gigabit Ethernet SOM PHY 10 USB OTG TYPE A Data Ctrl VBUS listed below SOM PHY 4 Power USB_VBUS_OTG Carrier 1 VADJ_13 Carrier 2 MGTAVCC Carrier 4 MGTAVTT Carrier 2 GND Carrier 25 TOTAL 100 PicoZed 7020 has 10 I O and PicoZed 7015 7030 adds 20 I O PicoZed 7015 7030 o...

Страница 22: ...evices of 2 or 3 are also capable of data transceiver rates up to 6 6Gb s in the SBG package Two differential MGT reference clock inputs are available for use with the GTP GTX lanes Either clock input can be used as the clock reference for any one or more of the GT lanes in bank 112 This allows the user to implement various protocols requiring different line rates Gigabit transceiver lanes and the...

Страница 23: ...ith the PC will remain persistent as long as the USB cable is plugged in The carrier may be power cycled or reset without loss of the port connection which is useful in the event a user wants to monitor the UART outputs on a terminal window Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP210x USB to UART bridge to appear as a COM port to host computer communicati...

Страница 24: ...ng the interface is in device mode Once connected the roles can change via the Host Negotiation Protocol HNP By default the PZCC FMC V2 ships in USB Host Mode with capacitors C76 C79 placed and R87 set to 10KΩ To change the mode from Host to OTG change R87 from 10KΩ to 1KΩ and remove capacitors C76 C79 To change the mode from Host to Device leave R87 at 10KΩ and remove capacitors C76 C79 USB Inter...

Страница 25: ... RJ45 connection The SOM s PHY is routed through JX3 directly to J1 For this reason the PHY is configured via the SOM The PZCC FMC V2 net names for this connector interface begin with PETH and are listed below SOM Net Name Carrier Net Name JX3 Pin PETH_PHY_LED0 PETH_PHY_LED0 47 PETH_PHY_LED1 PETH_PHY_LED1 48 PETH_MD1_P PETH_MD1_P 51 PETH_MD2_P PETH_MD2_P 52 PETH_MD1_N PETH_MD1_N 53 PETH_MD2_N PETH...

Страница 26: ...025E48 is used to store the MAC ID for the SOM s Ethernet PHY The device allows a user ID to be written at location 0x00 to 0x79 The devices remaining memory is programmed at the factory with a globally unique node address stored in the upper half of the array This address 0x80 to 0xFF is permanently write protected The I2C address is configured via JT5 and JT6 The default address is 0xA2 Figure 1...

Страница 27: ...ted Figure 14 MAC UNI O EEPROM 2 16 Real Time Clock Maxim DS3231MZ RTC I2C ADDR 0xD0 A Maxim DS3231 I2C RTC IC at address 0xD0 has been placed on the board to allow for clock and calendar functions The RTC has a built in oscillator so an external device is not required The interface is level translated using U11 a TCA9517 IC and attached to the HDMIO I2C bus The RTC has a battery backup using a BH...

Страница 28: ...eve part number BHX1 1025 included in PZCC FMC V2 KIT and firmly inserted into the carrier s socket The coin cell s positive terminal is placed into the opening of the sleeve facing up Please see figures below Figure 16 CR1025 battery placed in BHX1025 sleeve Figure 17 Battery sleeve orientation prior to insertion ...

Страница 29: ...CEC signal By default this component is not placed SOM Net Name Carrier Net Name JX1 Pin JX_SE_0 HDMIO_SCL 9 JX1_SE_1 HDMIO_SDA 10 JX1_LVDS_0_P HDMIO_CBCR5_D33 11 JX1_LVDS_1_P HDMIO_CBCR7_D35 12 JX1_LVDS_0_N HDMIO_CBCR4_D32 13 JX1_LVDS_1_N HDMIO_CBCR6_D34 14 JX1_LVDS_3_N HDMIO_SPDIF 20 JX1_LVDS_4_P HDMIO_HPD 23 JX1_LVDS_4_N HDMIO_PD 25 SOM Net Name Carrier Net Name JX2 Pin JX2_SE_0 HDMIO_CBCR0_D28...

Страница 30: ... range of 1 1 V to 3 6 V This allows the Zynq MIO and SDIO peripherals to operate at different supply voltages The microSD Card is connected through an 8 pin micro SD card connector J13 Molex 502570 0893 Note that this connector s supported temperature range is 25 to 85 C A Class 4 card or better is recommended Up to 32 GB is supported If a user intends to use the microSD card interface at industr...

Страница 31: ...t connection The port defaults to SOM JTAG operation unless an FMC board is placed Upon insertion of a FMC board the interface will switch the FMC into the JTAG chain via U3 A Xilinx JTAG platform cable HW USB II G or a Digilent JTAG HS2 or HS3 programming cable should be used when programming via these ports Diode D18 on the VREF pin is used to prevent the JTAG cable from back feeding into the PZ...

Страница 32: ...ce the maximum input voltage should not exceed 12 8V 12V 5 to minimize component stress thereby increasing the products operational life D19 and D20 are used for power steering in the event the user wants to insert the board into a PCIe x1 slot for development purposes Please Note While the PCIe slot can source 10 watts of power up to 25W via PC configuration it is recommended the carrier card be ...

Страница 33: ...with it removed Avnet has not tested power performance with this component removed Voltage V Tolerance IC Max DC current Functional area 12V Input 5 Wall adapter NOT ATX compatible 5 0A All power PCIe 12V Input 10 N A PCIe x1 card edge 10W 833 mA 25W 2083 mA All power 5V 5 U5 ADP2384ACP 3 0A SOM VIN Header VADJ 1 8V 2 5V or 3 3V For SOM VCCIO 13 34 35 NOTE For 7030 SOMs VADJ MUST be set to 1 8V ON...

Страница 34: ... may result This connection should be to a power supply or 1 5V battery The positive voltage is attached to pin 1 labeled BAT Ground is attached to pin 2 labeled GND See below figure Figure 22 JP1 VBAT connector 3 6 VADJ selection JP5 VADJ rail is configurable via JP5 VADJ is an independent rail supplying power to the Zynq PL I O banks and connected Pmods VADJ drives banks 34 and 35 WARNING When u...

Страница 35: ...ed or the PicoZed s PG_1V8 signal is de asserted VCCI_EN is driven low which turns off the FMC CC supplies 5V will continue to be supplied unless the power switch SW7 is set to OFF PG_CARRIER signal active high JX2 11 is pulled up by PicoZed s 3 3V PG_MODULE signal This signal can be pulled low by the carrier board SW4 the FMC board or the PicoZed when the board s power circuitry is not Good yet T...

Страница 36: ...ing Filtering The PZCC FMC V2 follows the recommended decoupling and layout techniques per each manufacturer s datasheet 3 9 PG Module Power Good LED A green status LED D4 illuminates when PG_CARRIER signal is high good Figure 24 PG_MODULE LED ...

Страница 37: ... interface Shared with SOMs eMMC JSFP1 JSFP1 Populated SFP interface signals breakout to this for connection J1 USB UART Populated Micro USB UART connection J2 12Vin N A 12V input J3 J5 MGTX1_P N Populated MGT SMA TX DATA J4 J6 MGTRX1_P N Populated MGT SMA RX DATA J7 JTAG Populated SOM FMC peripheral JTAG interface J8 USB OTG Populated USB 2 0 OTG Type A header J9 ETHERNET Populated SOM driven Gb ...

Страница 38: ... or 0 Default FMC address is 00 where the jumpers are placed at location 3 5 and 4 6 Figure 25 FMC Address select Carrier Net Name FMC LPC CON2E connection GA0 C34 GA1 D35 Table 22 FMC GA 1 0 address select 4 2 Clock Synthesizer test header The clock synthesizer has a test header which is not populated by default Users can monitor the synthesizer GPIO power I2C interface and interrupt See below fi...

Страница 39: ...tor points Figure 27 Voltage Monitor Connections 5 Mechanical 5 1 Diagram and Model A mechanical diagram and a 3D Model for the PZCC FMC V2 are available for download at www picozed org Product PicoZed FMC Carrier Card V2 Documentation under the Mechanical Drawings heading http picozed org support documentation 13076 5 2 Weight The weight of the PZCC FMC V2 with rubber feet SD card and jumpers pop...

Страница 40: ...40 22 Sept 2016 v1 1 6 Revision History Version date Ver Reason for change 26 Apr 2016 1 0 Initial release Table 23 Revision History ...

Страница 41: ...d a full transceiver to transceiver signal integrity check is performed Items between the transceivers such as board to board connectors interface connections ESD parts cables carrier layout practices etc must be carefully evaluated to ensure they can support the intended data rates without performance degradation For NON Standard protocols Avnet recommends using 5 0Gbps as a max data rate as this...

Страница 42: ...C This testing was performed to validate the SOMs operating range and not the carrier s therefore the carrier is not guaranteed to operate at this range yet Avnet has not had a failure in doing so III EMI Compliance There is no requirement for the PZCC FMC V2 to be tested to meet emissions compliance However there is a requirement for the PicoZed SOMs to meet emissions testing in which case the ca...

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