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Avnet PicoZed 7010, Руководство пользователя по оборудованию

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Avnet PicoZed 7010 Скачать руководство пользователя страница 17

 

 

3-Feb-2015 

16 

2.9  Configuration Modes 

Zynq-7000 AP SoC devices use a multi-stage boot process that supports both non-secure and 
secure boot. The PS is the master of the boot and configuration process. Upon reset, the device 
mode pins are read to determine the primary boot device to be used: NOR, NAND, Quad-SPI, SD 
Card or JTAG. PicoZed 7010/7020 allows 3 of those boot devices: QSPI is the default, while SD 
Card and JTAG boot are easily accessible by changing switch settings.  
 
Note: SD Card and JTAG interfaces should be implemented on the end user carrier card. 
 
Zynq has Voltage Mode pins, which are fixed on PicoZed 7010/7020 
 
The boot mode pins are shared with MIO[8:2]. The usage of these mode pins can be and are 
used as follows: 
 

 

MIO[2] / Boot_Mode[3]  

o

 

sets the JTAG mode 

 

MIO[5:3] / Boot_Mode[2:0]  

o

 

select the boot mode 

o

 

Boot_Mode[1] is fixed since it is only required for NOR boot, which is not 
supported on PicoZed 7010/7020 

 

MIO[6] / Boot_Mode[4]  

o

 

enables the internal PLL 

o

 

fixed to ‘enabled’ on PicoZed 7010/7020 

 

MIO[8:7] / Vmode[1:0] 

o

 

configures the I/O bank voltages 

o

 

fixed on PicoZed 7010/7020 

o

 

MIO Bank 0 / 500 (MIO[7] / Vmode[0]) set to ‘0’ for 3.3V 

o

 

MIO Bank 1 / 501 (MIO[8] / Vmode[1]) set to ‘1’ for 1.8V 

 
All mode pins are pulled either high 

or low through a 20 KΩ resistor that is either hard wired or 

connected to a switch or resistor jumper. By default, four mode signals are not jumper-adjustable 
and are populated as follows: 
 

 

MIO[3] / Boot_Mode[1] is pulled low 

via 20 KΩ resistor.   

 

MIO[6] / Boot_Mode[4] is 

pulled low via 20 KΩ resistor.  

 

MIO[7] / Vmode[0] is pulled low via 20 

KΩ resistor.   

 

MIO[8] / Vmode[1]  is pulled high via 20 

KΩ resistor.  

 
The other three mode signals, MIO[2], MIO[4] and MIO[5], are configurable via a jumper resistor 
or switch setting.  
 
MIO[2] is pulled either high or low via a 0 ohm resistor jumper JT4. Default setting from the 
factory is pulled low (position 1-2) and puts the Zynq in Cascade JTAG mode. 
 
MIO[5:4] is pulled high or low via a two channel dip switch SW1. Setting the switch positions will 
determine whether the Zynq boots from QSPI, the microSD card, or JTAG. 
 
The table below shows the available boot mode configuration setting using JT4 and SW1. 

 

 

 

Содержание PicoZed 7010

Страница 1: ...Zynq 7010 7020 SOM System On Module Hardware User Guide Version 1 4 2 3 2015 ...

Страница 2: ..._B INIT_B Pins 10 2 7 3 Processor Subsystem Reset 10 2 8 EXPANSION HEADERS 11 2 8 1 Micro Headers 11 2 9 CONFIGURATION MODES 16 2 9 1 JTAG Connections 17 2 10 POWER SUPPLIES 18 2 10 1 Voltage Rails and Sources 18 2 10 2 Voltage Regulators 19 2 10 3 Power Supply Sequencing 20 2 10 4 PCB Bypass Decoupling Strategy 22 2 10 5 Power Good LED 22 2 10 6 Power Estimation 22 2 10 7 XADC Power Configuration...

Страница 3: ...o 1 GB DDR3 x32 o 128 Mb QSPI Flash o 4GB eMMC Interfaces o 10 100 1000 Ethernet PHY Connector required on End User Carrier Card o USB 2 0 OTG PHY Connector required on End User Carrier Card o Three 100 pin Micro Headers On board Oscillator o 33 333 MHz Power o High efficiency regulators for VCCINT VCCPINT VCCBRAM VCCAUX VCCPAUX VCCPLL VCCO_0 VCCO_DDR VCCO_MIO1 and VCCO_MIO0 o VCCO_34 VCCO_35 and ...

Страница 4: ...tible inputs by default There is an option to support 1 5V capable DDR3 devices via a resistor change on the PicoZed 7010 7020 This option is provided as a note on the PicoZed 7010 7020 schematics DDR3L Termination is utilized on the PicoZed 7010 7020 and configured for fly by routing topology Additionally the board trace lengths are matched compensating for the XC7Z010 CLG400 internal package fli...

Страница 5: ...It can be used to initialize the PS subsystem as well as configure the PL subsystem bitstream Spansion provides Spansion Flash File System FFS for use after booting the Zynq 7000 AP SoC The relevant device attributes are 128Mbit o Optional densities are available via customization x1 x2 and x4 support Speeds up to 104 MHz supporting Zynq configuration rates 100 MHz o In Quad SPI mode this translat...

Страница 6: ...iplexer Select If the user wishes to use software to control the multiplexer select the Zynq PS_MIO0 pin is utilized When software controls the multiplexer select signal the running application can select either eMMC accesses for the Zynq or standard MIO interfaces via the JX2 connector When using software to control the multiplexer select signal the JX2 MIO interface becomes limited to 7 I O pins...

Страница 7: ...lone USB Transceiver Chip is used as the PHY The PHY features a complete HS USB Physical Front End supporting speeds of up to 480Mbs VDDIO for this device can be 1 8V or 3 3V and on the PicoZed 7010 7020 is powered at 1 8V The PHY is connected to MIO Bank 1 501 which is also powered at 1 8V This is critical since a level translator cannot be used as it would impact the tight ULPI timing required b...

Страница 8: ...d Other considerations need to be made to accommodate Host Mode Refer to the Avnet PicoZed FMC Carrier Card design for an example design for configuring the carrier card for either Host Mode or Device Mode Table 5 USB 2 0 Pin Assignment and Definitions Signal Name Description Zynq Bank MIO SMSC 3320 Pin Data 7 0 USB Data lines MIO Bank 1 501 28 39 Data 7 0 CLKOUT USB Clock MIO Bank 1 501 1 DIR ULP...

Страница 9: ...E1512 pin RX_CLK Receive Clock B17 16 27 46 RX_CTRL Receive Control D13 43 RXD 3 0 Receive Data RXD0 D11 RXD1 A16 RXD2 F15 RXD3 A15 44 45 47 48 TX_CLK Transmit Clock A19 53 TX_CTRL Transmit Control F14 56 TXD 3 0 Transmit Data TXD0 E14 TXD1 B18 TXD2 D10 TXD3 A17 50 51 54 55 MDIO Management Data C11 53 8 MDC Management Clock C10 52 7 ETH_RST_N PHY Reset B14 47 16 Requires a resistor change to the b...

Страница 10: ... 501 JX3 34 PS_MIO42 E12 MIO Bank 501 JX3 37 PS_MIO43 A9 MIO Bank 501 JX3 36 PS_MIO44 F13 MIO Bank 501 JX3 39 PS_MIO45 B15 MIO Bank 501 JX3 38 PS_MIO46 D16 MIO Bank 501 JX3 41 PS_MIO47 B14 MIO Bank 501 JX3 40 PS_MIO48 B12 MIO Bank 501 JX3 42 PS_MIO49 C12 MIO Bank 501 JX3 44 PS_MIO50 B13 MIO Bank 501 JX3 66 PS_MIO51 B9 MIO Bank 501 JX3 64 2 5 2 Available PL IO User Pins PicoZed 7010 7020 provides 5...

Страница 11: ..._B or INIT_B is capable of doing this as in other Xilinx FPGA architectures 2 7 2 PROGRAM_B DONE PUDC_B INIT_B Pins INIT_B PROGRAM_B and PUDC_B all have pull up resistors to appropriate voltages applied to them The INIT_B PUDC_B and DONE signals are routed to the carrier card via the Micro Headers JX1 and JX2 There is not a DONE LED indicator on the PicoZed 7010 7020 System On Module When PL confi...

Страница 12: ...he flexibility to control the I O bank voltages Separate routes planes are used for VCCO_34 and VCCO_35 such that the carrier card could potentially power these independently The PicoZed 7010 has two PL I O banks Banks 34 and 35 each contain 50 I O The PicoZed 7020 contains a third PL I O bank Bank 13 is fully connected 25 I O on the PicoZed 7020 Bank 13 s power has an independent rail VCCO_13 whi...

Страница 13: ...pansion 1 Analog VP_0 Zynq Bank 0 4 Vin Expansion 5 VN_0 Zynq Bank 0 GND Expansion 23 DXP_0 Zynq Bank 0 VCCO_35 Expansion 3 DXN_0 Zynq Bank 0 VCCO_13 Expansion 1 C FPGA_DONE Zynq Bank 0 2 PUDC_B IO Zynq Bank 34 TOTAL 100 PWR_Enable Expansion 1 Vin Expansion 4 GND Expansion 23 VCCO_34 Expansion 3 VBATT Expansion 1 TOTAL 100 Table 9 Micro Header JX3 Pin Out Micro Header 3 JX3 Signal Name Source Pins...

Страница 14: ...LVDS_10_N 43 44 JX1_LVDS_11_N 34 U19 N A GND 45 46 GND N A 34 N18 JX1_LVDS_12_P 47 48 JX1_LVDS_13_P 34 N20 34 P19 JX1_LVDS_12_N 49 50 JX1_LVDS_13_N 34 P20 N A GND 51 52 GND N A 34 T20 JX1_LVDS_14_P 53 54 JX1_LVDS_15_P 34 V20 34 U20 JX1_LVDS_14_N 55 56 JX1_LVDS_15_N 34 W20 N A VIN_HDR 57 58 VIN_HDR N A N A VIN_HDR 59 60 VIN_HDR N A 34 Y18 JX1_LVDS_16_P 61 62 JX1_LVDS_17_P 34 V16 34 Y19 JX1_LVDS_16_...

Страница 15: ...DS_9_N 35 J19 N A GND 45 46 GND N A 35 L16 JX2_LVDS_10_P 47 48 JX2_LVDS_11_P 35 K17 35 L17 JX2_LVDS_10_N 49 50 JX2_LVDS_11_N 35 K18 N A GND 51 52 GND N A 35 H16 JX2_LVDS_12_P 53 54 JX2_LVDS_13_P 35 J18 35 H17 JX2_LVDS_12_N 55 56 JX2_LVDS_13_N 35 H18 N A VIN_HDR 57 58 VIN_HDR N A N A VIN_HDR 59 60 VIN_HDR N A 35 G17 JX2_LVDS_14_P 61 62 JX2_LVDS_15_P 35 F19 35 G18 JX2_LVDS_14_N 63 64 JX2_LVDS_15_N 3...

Страница 16: ...C12 N A VCCO_13 45 46 VCCO_13 N A N A ETH_PHY_LED0 47 48 ETH_PHY_LED1 N A N A GND 49 50 GND N A N A ETH_MD1_P 51 52 ETH_MD2_P N A N A ETH_MD1_N 53 54 ETH_MD2_N N A N A GND 55 56 GND N A N A ETH_MD3_P 57 58 ETH_MD4_P N A N A ETH_MD3_N 59 60 ETH_MD4_N N A N A GND 61 62 GND N A N A USB_OTG_ID 63 64 PS_MIO51 501 B9 N A GND 65 66 PS_MIO50 501 B13 N A USB_OTG_P 67 68 USB_VBUS_OTG N A N A USB_OTG_N 69 70...

Страница 17: ...xed to enabled on PicoZed 7010 7020 MIO 8 7 Vmode 1 0 o configures the I O bank voltages o fixed on PicoZed 7010 7020 o MIO Bank 0 500 MIO 7 Vmode 0 set to 0 for 3 3V o MIO Bank 1 501 MIO 8 Vmode 1 set to 1 for 1 8V All mode pins are pulled either high or low through a 20 KΩ resistor that is either hard wired or connected to a switch or resistor jumper By default four mode signals are not jumper a...

Страница 18: ...resistor RP2 2 but also connected to the Micro Header Program_B is pulled high via a 4 7KΩ resistor RP2 4 CFGBVS is pulled high via a 4 7KΩ resistor RP2 1 The PS is responsible for configuring the PL Zynq will not automatically reconfigure the PL as in standard FPGAs by toggling PROG Likewise it is not possible to hold off Zynq boot up with INIT_B as this is now done with POR If the application ne...

Страница 19: ...card via the VIN pins on the Micro Headers and are expected to carry 5V or 12V to the PicoZed System On Module for the input to the regulators There are also three bank voltages that are supplied from the end user carrier card to the PicoZed System On Module Bank 34 VCCO_34 Bank 35 VCCO_35 and Bank 13 VCCO_13 are generated on the end user carrier card and connected to the PicoZed 7010 7020 System ...

Страница 20: ...ing power solution provides the power rails of the PicoZed 7010 7020 Sequencing of the supplies is implemented by cascading the POWER GOOD outputs of each supply to the ENABLE input for the next supply in the sequence 3 3V is the last supply to come up therefore the POWER GOOD for the 3 3V supply is used to drive the PG_MODULE net and is used as the power on reset control for Zynq U11 pin C7 Ether...

Страница 21: ...ltage Rails w Max Output Current TI Part Number Voltage V Max Current A TLV62130 1 0 3 TLV62130 1 8 3 TLV62130 1 35 3 TLV62130 3 3 3 TPS51206 0 675 2 2 10 3 Power Supply Sequencing When attached to an end user carrier card the carrier card must provide an active high power enable signal PWR_ENABLE This controls the first PicoZed 7010 7020 regulator U19 1 0V turning on This should be an open drain ...

Страница 22: ...e if connected to an end user carrier card the 1 8V power supply s power good output should is used as the enable to the VCCIO regulators via the PG_1V8 VCCIO_EN signal on the Micro Headers The following diagram illustrates sequencing with an expansion card Figure 8 Power Sequencing with Carrier Card ...

Страница 23: ... design_tools logic_design xpe htm When designing the PicoZed 7010 7020 power system this tool was used to ensure that the SOM system could supply enough power to the Zynq and its on board peripherals using worst case parameters including logic utilization operating frequency and temperature Since the power supply for the VCCIO rails for banks 34 35 and 13 are supplied from the carrier card it is ...

Страница 24: ...to net FPGA_VBATT and is tied through a 0 Ω resistor R14 to the PicoZed VCCAUX supply which is 1 8V However FPGA_VBATT is also extended to the end user carrier card To apply an external battery to Zynq from the end user carrier card the 0 ohm resistor R14 should be removed from the PicoZed System On Module 2 10 9 Cooling Fan An unpopulated header JP1 labeled FAN is available in the event a fan is ...

Страница 25: ...Purpose 13 0 9 40 46 48 51 TOTAL 54 The Micro Header GPIO assignments aren t specifically defined interfaces such as those that are defined in Table 17 The table below provides the MIO locations of the PS MIO general purpose pins and the functions that they are intended to support The end user is encouraged to utilize the Zynq TRM in defining the MIO peripheral mappings that they would like to uti...

Страница 26: ...r Card Vcco_35 Bank 13 Carrier Card Vcco_13 PL I O Banks 34 35 and 13 are powered from the end user carrier card These bank supplies are designed to be independent on the PicoZed 7010 7020 Maximum flexibility is allowed to the designer for these banks as the voltage level and standards are left to the end user carrier card design The designer of the end user carrier card VCCO supplies is provided ...

Страница 27: ...d 7010 7020 measures 2 25 x 4 00 57 15 mm x 101 6 mm Figure 12 PicoZed 7010 7020 Top View Mechanical Dimensions PicoZed 7010 7020 has a maximum vertical dimension of 0 366 9 3mm Figure 13 PicoZed 7010 7020 Side View Vertical Dimension ...

Страница 28: ...itial PicoZed 7010 7020 Hardware User Guide 30 Oct 14 1 1 DDR3L documented and Diagram Updates 2 Dec 14 1 2 Diagram Update Figure 5 and PL IO LVDS support 8 Dec 14 1 3 Removed AR numbers for DDR3 and reference UG933 3 Feb 15 1 4 Swapper JX3 pin listing in Table 7 for JX3 64 JX3 66 ...

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