background image

 

 

AL462B-EVB-A0-User Manual 

 

 

©2018 Copyright by AverLogic Technologies, Corp.                                                                              Version 1.0

 

             

 

4

 

1 Introduction 

The  AL462  HSMC  EVB  is  designed  for  connecting  the  AL462  chip  to  an  ALTERA  FPGA 

board. This configuration facilitates design verification/validation when developing or testing 

with the AL462 chip.  

The  HSMC  connector  is  a  modified  version  of  a  standard  high-speed  Samtec  connector, 

which is pin-to-pin compatible with the Cyclone V 

FPGA host board’s HSMC connector.  

We  also  provide  an  FPGA  sample  code  for  Cyclone  V  GX  Kit.  Please  contact  your 

AverLogic representative for more information. 

 

1.1 EVB Content 

 

 

 

 

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 

 

Evaluation Board

 

5V Power Adapter

 

Содержание AL462B-EVB-A0

Страница 1: ...ORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE HOWEVER NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS USE OR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF AVERLOGIC 2018 by AverLogic Technologies Corp ...

Страница 2: ...CE AVERLOGIC TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN AVERLOGIC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS CUSTOMERS ARE ADVISED TO CONSULT WITH AVERLOGI...

Страница 3: ...ies Corp Version 1 0 3 Table of Contents 1 INTRODUCTION 4 1 1 KIT CONTENT 4 2 EVB CONTROL INTERFACE 5 2 1 BOARD VIEW 5 2 2 USER CONTROL INTERFACE 6 3 ADAPTOR INTERFACE 7 3 1 ALTERA HSMC CONNECTOR 7 3 2 J1 J3 DEBUG PORT 40 PIN HEADERS 9 4 MECHANICAL SPECIFICATION 10 ...

Страница 4: ... design verification validation when developing or testing with the AL462 chip The HSMC connector is a modified version of a standard high speed Samtec connector which is pin to pin compatible with the Cyclone V FPGA host board s HSMC connector We also provide an FPGA sample code for Cyclone V GX Kit Please contact your AverLogic representative for more information 1 1 EVB Content Evaluation Board...

Страница 5: ...8 Copyright by AverLogic Technologies Corp Version 1 0 5 2 EVB Control Interface 2 1 Board View Top Side Bottom Side HSMC Connector 1 Short Open AL462 J3 J1 J4 J5 J6 S2 S1 JP1 JP2 ST1 ST2 ST3 ST4 ST5 ST6 S3 J2 SW1 J7 Bottom On Off ...

Страница 6: ...OE0 and OE1 enable pins Short On S3 Power Switch JP1 Reserved for I O Power JP2 Reserved for I O Power ST1 1 8 DL_CFG_0 2 7 DL_CFG_1 3 6 DL_CFG_1 4 5 TMOD_2 Open Off Open Off Open Off Open Off ST2 1 8 D_CFG_4 2 7 D_CFG_5 3 6 RCKOINV_0 4 5 RCKOINV_1 Open Off Open Off Open Off Open Off ST3 1 8 D_CFG_4 2 7 D_CFG_5 3 6 RCKOINV_0 4 5 RCKOINV_1 Open Off Open Off Open Off Open Off ST4 1 8 RCKO_0 2 7 RCKO...

Страница 7: ..._12 HSMC_DI_12 J1 8 HSMC_DI_Ch1_12 50 DI_27 HSMC_DI_27 J1 9 HSMC_DI_Ch2_11 53 DI_11 HSMC_DI_11 J1 10 HSMC_DI_Ch1_11 54 DI_26 HSMC_DI_26 J1 11 HSMC_DI_Ch2_10 55 DI_10 HSMC_DI_10 J1 12 HSMC_DI_Ch1_10 56 DI_25 HSMC_DI_25 J1 13 HSMC_DI_Ch2_09 59 DI_09 HSMC_DI_09 J1 14 HSMC_DI_Ch1_09 60 DI_24 HSMC_DI_24 J1 15 HSMC_DI_Ch2_08 61 DI_08 HSMC_DI_08 J1 16 HSMC_DI_Ch1_08 62 DI_23 HSMC_DI_23 J1 17 HSMC_DI_Ch2_...

Страница 8: ...9 HSMC_DO_09 J3 14 HSMC_DO_CH1_09 120 DO_24 HSMC_DO_24 J3 15 HSMC_DO_CH2_08 121 DO_08 HSMC_DO_08 J3 16 HSMC_DO_CH1_08 122 DO_23 HSMC_DO_23 J3 17 HSMC_DO_CH2_07 125 DO_07 HSMC_DO_07 J3 18 HSMC_DO_CH1_07 126 DO_22 HSMC_DO_22 J3 19 HSMC_DO_CH2_06 127 DO_06 HSMC_DO_06 J3 20 HSMC_DO_CH1_06 128 DO_21 HSMC_DO_21 J3 21 HSMC_DO_CH2_05 131 DO_05 HSMC_DO_05 J3 22 HSMC_DO_CH1_05 132 DO_20 HSMC_DO_20 J3 23 HSM...

Страница 9: ...ies Corp Version 1 0 9 The HSMC connector pin map for the adaptor is illustrated in the figure below Figure HSMC Connector Pin Map 3 2 J1 J3 Debug Port 40 pin Headers The pin maps for the two headers are shown in the figure below Figure Two Debug Port Pin Map J1 J3 ...

Страница 10: ...AL462B EVB A0 User Manual 2018 Copyright by AverLogic Technologies Corp Version 1 0 10 4 Mechanical Specification Diagram 150mm 150mm 164mm 35 6mm 35 6mm ...

Страница 11: ...AL462B EVB A0 User Manual 2018 Copyright by AverLogic Technologies Corp Version 1 0 11 CONTACT INFORMATION Averlogic Technologies Corp E mail sales averlogic com URL http www averlogic com ...

Отзывы: