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Maintenance Object Repair Procedures
555-233-123 10-1494 Issue 4 May 2002
SHDW-LNK (Memory Shadowing
Link)
A High or Critical Reliability system contains two SPEs. One is known as the
Active SPE and is the SPE that is currently responsible for all call processing,
administration, and maintenance activities being performed by the system. The
other SPE is known as the Standby SPE. The role of the Standby SPE is to be
ready to take over as the Active SPE in the event that the current Active SPE fails.
The Standby SPE is usually in a mode known as Standby Mode in which it is
ready to assume the role of the Active SPE. To do this, Standby SPE Memory
(MEM-BD) must be an up-to-date reflection of Active SPE Memory. This is
accomplished via the memory shadowing mechanism described below.
The SHDW-CIR (Common Shadow Circuit) on the Active SPE Duplication
Interface circuit pack (DUPINT, TN772) detects all memory writes that the Active
SPE Processor (PROCR) makes to Active SPE Memory. The Active SPE
Common Shadow Circuit sends this information to the Common Shadow Circuit
on the Standby SPE Duplication Interface circuit pack via the Inter-Carrier Cable
(ICC). The Common Shadow Circuit on the Standby SPE Duplication Interface
circuit pack then writes the data to Standby SPE Memory. This logical connection
between Active SPE Memory and Standby SPE Memory is known as the
SHDW-LNK (Memory Shadowing Link).
Although most of the components comprising the Memory Shadowing Link (that
is, Active SPE Memory, both sets of Common Shadow Circuit, and Standby SPE
Memory) may be tested individually, it is useful to test the integrity of the entire
logical connection to verify that the shadowing mechanism is functional and that
Standby SPE Memory is the same as Active SPE Memory. Therefore, this testing
is done under the guise of the Memory Shadowing Link.
The logical connection between the Memory circuit packs of the two SPEs of a
High or Critical Reliability system is shown in
Figure 10-88 on page 10-1495 . This
connection includes the A carrier memory bus, the A carrier TN772 Duplication
Interface circuit pack, the shadow extension in the ICC, the B carrier TN772
Duplication Interface circuit pack, and the B carrier memory bus. The dotted lines
in
Figure 10-88 on page 10-1495 represent important logical connections between
components. The following circuit pack abbreviations are used in Figure 10-88 on
page 10-1495 :
■
DUPINT for Duplication Interface circuit pack
■
PI for Processor Interface
■
Net Pkt for Network Controller/Packet Interface
MO Name (in
Alarm Log)
Alarm
Level
Initial Command to
Run Full Name of MO
SHDW-LNK MAJOR test shadow-link Memory Shadowing Link