Atten ATM3500A, Руководство пользователя

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Enable the bus controller’s IEEE-488 SRQ interrupt.
Procedures to Determine When a Command Sequence is Completed.
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Clear the DMM’s output buffer by sending a device clear message.
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Clear the event registers by using *CLS command.
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Enable “operation complete” by using the *ESE 1 command.
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Send the *OPC? command and enter the result to enable
synchronization.
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When bit 5 is set in the status byte summary register, please use a
serial poll to check. Then you could set the DMM for an SRQ
interrupt by using *SRE 32.
Usage of the Messages Available Bit (MAV)
You can use the status byte “message available bit 4” to decide when
data is available to read in the bus controller. When the first reading
trigger occurs by using the command TRIGger:SOURce:IMMediate, the
DMM will automatically enable the bit 4. The DMM will clear bit 4 only
after entire messages have been read from the output buffer.
The MAV bit can indicate only when the first reading is generated by
the READ? command. So this will be helpful for you as a trigger event
such as BUS or EXTernal will occur. In addition, the MAV bit is set only
after all specified measurements have completed by using the INITiate
and FETCH? commands. That means in detail, the INITIate command
is used to store readings in the DMM’s internal memory. And the
FETCH? command is used to transfer readings to the DMM’s output
buffer.
Signal by Using *OPC When Data is in the Output Buffer
Normally, to use the “operation complete bit 0” in the standard event
register will signal as a command sequence is completed. The bit is set
in the register after executing an *OPC command. And if you send an
*OPC after a command loading a message in the DMM’s output buffer,
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