Atten ATM3500A, Руководство пользователя

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Bit Decimal
Value
Definition
0.
Not Used
1 Set to 0.
1.
Not Used
2 Set to 0.
2.
Not Used
4 Set to 0.
3.
Questionable Data
8 One or more bits are set in the questionable data register (Bits
have to be “enabled” in enable register).
4.
Message Available
16 Data in the DMM’s output buffer is available.
5.
Standard Event
32 One or more bits are set in the Standard Event Register (Bits have
to be “enabled” in enable register).
6.
Request Service
64 The DMM is requiring service (Serial Poll).
7.
Not Used
128 Set to 0.
On the other hand, there are some conditions that you have to note.
The following conditions will clear the summary register.

You execute a *CLS (clear status) command.

To query the standard event and questionable data registers will
clear only the separate bits in the summary register.
The following conditions will clear the enable register.

You turn on the power, and have set the DMM previously by using
the *PSC 1 command.

You execute a *SRE 0 command.
Note: If you have set the DMM previously by using *PSC 0, the
※
status byte enable register won’t be cleared at power-on.
How to use SRQ (Service Request) and Serial Poll
You have to set your bus controller to repond to the IEEE-488 SRQ and
interrupt to use this capability. Use the status byte enable register
(SRE) to select the low-level IEEE-488 SRQ signal set by summary
bits. As the status byte bit 6 is set, an IEEE-488 SRQ interrupt
message will be sent automatically to the bus controller which may poll
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