Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 27-8. Fast Startup Circuitry
Each wake-up input pin and alarm can be enabled to generate a Fast Startup event by writing 1
to the corresponding bit in the Fast Startup Mode Register PMC_FSMR.
The user interface does not provide any status for Fast Startup, but the user can easily recover
this information by reading the PIO Controller and the status registers of the RTC, RTT and USB
Controller.
27.2.12 Main Crystal Clock Failure Detector
The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscilla-
tor to identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the
clock failure detector is disabled too.
The slow RC oscillator must be enabled.The clock failure detection must be enabled only when
system clock MCK selects the fast RC oscillator. Then the status register must be read 2 slow
clock cycles after enabling.
A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal
is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1
fast_restart
WKUP15
FSTT15
FSTP15
WKUP1
FSTT1
FSTP1
WKUP0
FSTT0
FSTP0
RTTAL
RTCAL
USBAL
RTT Alarm
RTC Alarm
USB Alarm