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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
17.4.2
Slow Clock Generator
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power
supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC
oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow
clock to be valid in a short time (about 100 µs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more
accurate frequency. The command is made by writing the Supply Controller Control Register
(SUPC_CR) with the XTALSEL bit at 1.This results in a sequence which first configures the PIO
lines multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then enables the crystal
oscillator, then counts a number of slow RC oscillator clock periods to cover the startup time of
the crystal oscillator (refer to electrical characteristics for details of 32KHz crystal oscillator
startup time), then switches the slow clock on the output of the crystal oscillator and then dis-
ables the RC oscillator to save power. The switching time may vary according to the slow RC
oscillator clock frequency range. The switch of the slow clock source is glitch free. The OSCSEL
bit of the Supply Controller Status Register (SUPC_SR) allows knowing when the switch
sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left
unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In
this case, the user has to provide the external clock signal on XIN32. The input characteristics of
the XIN32 pin are given in the product electrical characteristics section. In order to set the
bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs
to be set at 1.
17.4.3
Voltage Regulator Control/Backup Low Power Mode
The Supply Controller can be used to control the embedded 1.8V voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load
current. Please refer to the electrical characteristics section.
The programmer can switch off the voltage regulator, and thus put the device in Backup mode,
by writing the Supply Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This can be done also by using WFE (Wait for Event) Cortex-M processor instruction with the
deep mode bit set to 1.
The Backup mode can also be entered by executing the WFI (Wait for Interrupt) or WFE (Wait for
Event) Cortex-M Processor instructions. To select the Backup mode entry mechanism, two
options are available, depending on the SLEEPONEXIT bit in the Cortex-M processor System
Control register:
• Sleep-now: if the SLEEPONEXIT bit is cleared, the device enters Backup mode as soon as
the WFI or WFE instruction is executed.
• Sleep-on-exit: if the SLEEPONEXIT bit is set when the WFI instruction is executed, the
device enters Backup mode as soon as it exits the lowest priority ISR.
This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the
worse case, two slow clock cycles. Once the vddcore_nreset signal is asserted, the processor
and the peripherals are stopped one slow clock cycle before the core power supply shuts off.
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