20
8331B–AVR–03/12
Atmel AVR XMEGA AU
4.
Memories
4.1
Features
•
Flash program memory
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
•
Data memory
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
– External memory support
SRAM
SDRAM
Memory mapped external hardware
– Bus arbitration
Deterministic handling of priority between CPU, DMA controller, and other bus masters
– Separate buses for SRAM, EEPROM, I/O memory, and external memory access
Simultaneous bus access for CPU and DMA controller
•
Production signature row memory for factory programmed data
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
•
User signature row
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
4.2
Overview
This section describes the different memory sections. The AVR architecture has two main mem-
ory spaces, the program memory and the data memory. Executable code can reside only in the
program memory, while data can be stored in the program memory and the data memory. The
data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All mem-
ory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM)
spaces can be locked for further write and read/write operations. This prevents unrestricted
access to the application software.
