AT90S/LS4434 and AT90S/LS8535
25
General Interrupt Flag Register – GIFR
•
Bit 7 – INTF1: External Interrupt Flag1
When an edge or logical change on the INT1 pin trigger an interrupt request, INTF1 becomes set (one). This flag is always
cleared (0) when the pin is configured for low-level interrupts, as the state of a low-level interrupt can be determined by
reading the PIN register.
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt address $002. For edge and
logic change interrupts, this flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical “1” to it.
•
Bit 6 – INTF0: External Interrupt Flag0
When an edge or logical change on the INT0 pin trigger an interrupt request, INTF0 becomes set (one). This flag is always
cleared (0) when the pin is configured for low-level interrupts, as the state of a low-level interrupt can be determined by
reading the PIN register.
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt address $001. For edge and
logic change interrupts, this flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical “1” to it.
•
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4434/8535 and always read as zero.
Timer/Counter Interrupt Mask Register – TIMSK
•
Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-
rupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e.,
when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
•
Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the
TOV2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
•
Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a capture-triggering event occurs on pin 20,
PD6 (ICP) (i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
•
Bit 4 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a CompareA match in Timer/Counter1
occurs (i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
•
Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector $007) is executed if a CompareB match in Timer/Counter1
occurs (i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
–
–
–
–
–
–
GIFR
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$39 ($59)
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
–
TOIE0
TIMSK
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial value
0
0
0
0
0
0
0
0
