Atmel AT90S8414, Руководство пользователя

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AT90S8414
Preliminary
4-19
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL
Figure 19: Relative Program Memory Addressing
Program execution continues at address PC + k. The relative address k is
±
2K.
The EEPROM Data Memory
The AT90S8414 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between
the EEPROM and the CPU is described on Page 4-44 specifying the EEPROM address register, the EEPROM data
register, and the EEPROM control register.
For the SPI data downloading, see Page 4-75 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The
AVR
CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No
internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
System Clock Ø
T1 T2 T3 T4
1’st Instruction Fetch
1’st Instruction Execute
2’nd Instruction Fetch
2’nd Instruction Execute
3’rd Instruction Fetch
3’rd Instruction Execute
4’th Instruction Fetch
Figure 20: The Parallel Instruction Fetches and Instruction Executions