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Atmel AT90S1200 Скачать руководство пользователя страница 45

45

AT90S1200

0838H–AVR–03/02

3.

If a Chip Erase is performed (must be done to erase the Flash), wait t

WD_ERASE

after the instruction, give RESET a positive pulse, and start over from step 2.
See Table 21 on page 47 for t

WD_ERASE

value.

4.

The Flash or EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before new data is written. Wait
t

WD_PROG

after transmitting the instruction. In an erased device, no $FFs in the

data file(s) needs to be programmed. See Table 22 on page 47 for t

WD_PROG

value.

5.

Any memory location can be verified by using the Read instruction which returns
the content at the selected address at the serial output MISO (PB6) pin.

At the end of the programming session, RESET can be set high to commence nor-
mal operation.

6.

Power-off sequence (if needed):

Set XTAL1 to “0” (if a crystal is not used or the device is running from the Internal
RC Oscillator).

Set RESET to “1”.

Turn V

CC

power off.

Data Polling EEPROM

When a byte is being programmed into the EEPROM, reading the address location
being programmed will give the value P1 until the auto-erase is finished, and then the
value P2. See Table 18 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time

t

WD_PROG

before programming the next byte. See Table 22

for

t

WD_PROG

value. As a chip-erased device contains $FF in all locations, programming of

addresses that are meant to contain $FF can be skipped. This does not apply if the
EEPROM is reprogrammed without first chip-erasing the device.

Data Polling Flash

When a byte is being programmed into the Flash, reading the address location being
programmed will give the value $FF. At the time the device is ready for a new byte, the
programmed value will read correctly. This is used to determine when the next byte can
be written. This will not work for the value $FF, so when programming this value, the
user will have to wait for at least t

WD_PROG

before programming the next byte. As a chip-

erased device contains $FF in all locations, programming of addresses that are meant
to contain $FF, can be skipped.

Table 18.

Read Back Value during EEPROM Polling

Part

P1

P2

AT90S1200

$00

$FF

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Содержание AT90S1200

Страница 1: ...p Analog Comparator Programmable Watchdog Timer with On chip Oscillator SPI Serial Interface for In System Programming Special Microcontroller Features Low power Idle and Power down Modes External and...

Страница 2: ...cessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontroller...

Страница 3: ...0 mA and thus drive LED displays directly When pins PB0 to PB7 are used as inputs and are externally pulled low they will source current if the internal pull up resistors are activated The Port B pins...

Страница 4: ...clock source If enabled the AT90S1200 can operate with no external compo nents A control bit RCEN in the Flash Memory selects the On chip RC Oscillator as the clock source when programmed 0 The AT90S1...

Страница 5: ...a register Single register operations are also executed in the ALU Figure 4 shows the AT90S1200 AVR RISC microcontroller architecture The AVR uses a Har vard architecture concept with separate memorie...

Страница 6: ...e only exception is the five constant arithmetic and logic instructions SBCI SUBI CPI ANDI ORI between a constant and a register and the LDI instruction for load immediate constant data These instruct...

Страница 7: ...the operation code part of the instruction word To simplify not all figures show the exact location of the addressing bits Register Direct Single Register Rd Figure 6 Direct Single Register Addressing...

Страница 8: ...Stack The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts The hardware stack is 9 bits wide and stores the Program Counter PC return address while subroutines and interrupt...

Страница 9: ...ision is used Figure 11 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access register file concept This is the basic pipe lining co...

Страница 10: ...y writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read as set thus clearing the flag The CBI and SBI...

Страница 11: ...the Instruction Set description for detailed information Bit 4 S Sign Bit S N V The S bit is always an exclusive or between the negative flag N and the two s comple ment overflow flag V See the Instru...

Страница 12: ...Sources The AT90S1200 has three sources of reset Power on Reset The MCU is reset when the supply voltage is below the power on Reset threshold VPOT External Reset The MCU is reset when a low level is...

Страница 13: ...onnected to VCC directly or via an external pull up resistor By holding the RESET pin low for a period after VCC has Table 3 Reset Characteristics VCC 5 0V Symbol Parameter Min Typ Max Units VPOT 1 Po...

Страница 14: ...uaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage VRST on its positive edge the delay timer starts the MCU after the Time out period tTOUT has expired Figure 16...

Страница 15: ...ion s to be cleared If an interrupt condition occurs when the corresponding interrupt enable bit is cleared zero the interrupt flag will be set and remembered until the interrupt is enabled or the fla...

Страница 16: ...is enabled The corresponding interrupt at vector 002 is executed if an overflow in Timer Counter0 occurs i e when the TOV0 bit is set in the Timer Counter Interrupt Flag Register TIFR Bit 0 Res Reserv...

Страница 17: ...ponse for all the enabled AVR interrupts is four clock cycles minimum Four clock cycles after the interrupt flag has been set the program vector address for the actual interrupt handling routine is ex...

Страница 18: ...1 ISC00 Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask in the GIMSK register is set Th...

Страница 19: ...ts as well as internal ones like Timer Overflow interrupt and Watchdog Reset If wakeup from the Analog Comparator interrupt is not required the Analog Comparator can be powered down by setting the ACD...

Страница 20: ...r as a Counter with an external pin connection which triggers the counting Timer Counter0 Prescaler Figure 18 shows the general Timer Counter0 prescaler Figure 18 Timer Counter0 Prescaler The four dif...

Страница 21: ...ynchronized with the oscillator frequency of the CPU To assure proper sampling of the external clock the minimum time between two external clock transitions must be at least one internal CPU clock per...

Страница 22: ...s feature can give the user SW control of the counting Timer Counter0 TCNT0 The Timer Counter0 is realized as an up counter with read and write access If the Timer Counter0 is written and a clock sour...

Страница 23: ...es without another WDR instruction the AT90S1200 resets and executes from the Reset Vector For timing details on the Watchdog Reset refer to page 14 Figure 20 Watchdog Timer Watchdog Timer Control Reg...

Страница 24: ...Reset the Watchdog Timer may not start to count from zero To avoid unintentional MCU resets the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select Table 6 Wa...

Страница 25: ...When the EEPROM is read or written the CPU is halted for two clock cycles before the next instruction is executed EEPROM Address Register EEAR Bit 7 6 Res Reserved Bits These bits are reserved bits in...

Страница 26: ...write operation to avoid these problems Prevent EEPROM Corruption During periods of low VCC the EEPROM data can be corrupted because the supply volt age is too low for the CPU and the EEPROM to operat...

Страница 27: ...ive and Idle modes When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 Res Reserv...

Страница 28: ...arator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator Interrupt The different settings are shown in Table 7 Note When changing the ACIS1 ACIS0 bits th...

Страница 29: ...B pins with alternate functions are shown in Table 8 When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate function description Port B...

Страница 30: ...of Port B are SCK Port B Bit 7 SCK Clock Input pin for memory up downloading MISO Port B Bit 6 MISO Data Output pin for memory uploading MOSI Port B Bit 5 MOSI Data Input pin for memory downloading A...

Страница 31: ...AT90S1200 0838H AVR 03 02 Port B Schematics Note that all port pins are synchronized The synchronization latches are however not shown in the figures Figure 22 Port B Schematic Diagram Pins PB0 and P...

Страница 32: ...32 AT90S1200 0838H AVR 03 02 Figure 23 Port B Schematic Diagram Pins PB2 PB3 and PB4 Figure 24 Port B Schematic Diagram Pin PB5 2...

Страница 33: ...33 AT90S1200 0838H AVR 03 02 Figure 25 Port B Schematic Diagram Pin PB6 Figure 26 Port B Schematic Diagram Pin PB7...

Страница 34: ...he pins are read Port D as General Digital I O PDn general I O pin The DDDn bit in the DDRD Register selects the direction of this pin If DDDn is set one PDn is configured as an output pin If DDDn is...

Страница 35: ...e the interrupt description for further details Port D Schematics Note that all port pins are synchronized The synchronization latches are however not shown in the figures Figure 27 Port D Schematic D...

Страница 36: ...Pin PD2 Figure 29 Port D Schematic Diagram Pin PD4 DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PD4 R R WP WD RL RP RD WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD DDD4 PO...

Страница 37: ...are 1 00 1E indicates manufactured by Atmel 2 01 90 indicates 1 Kb Flash memory 3 02 01 indicates AT90S1200 device when 01 is 90 Note When both Lock bits are programmed lock mode 3 the signature byte...

Страница 38: ...mes The XA1 XA0 pins determines the action executed when the XTAL1 pin is given a posi tive pulse The coding is shown in Table 15 When pulsing WR or OE the command loaded determines the action execute...

Страница 39: ...DATA to 1000 0000 This is the command for Chip Erase 4 Give XTAL1 a positive pulse This loads the command 5 Give WR a tWLWH_CE wide negative pulse to execute Chip Erase tWLWH_CE is found in Table 17...

Страница 40: ...it until RDY BSY goes high to program the next byte See Figure 31 for signal waveforms F Load Data High Byte 1 Set XA1 XA0 to 01 This enables data loading 2 Set DATA Data high byte 00 FF 3 Give XTAL1...

Страница 41: ...ash for details on command and address loading 1 A Load Command 0000 0010 2 B Load Address High Byte 00 01 3 C Load Address Low Byte 00 FF 4 Set OE to 0 and BS to 0 The Flash word low byte can now be...

Страница 42: ...e Bit 7 6 4 1 1 These bits are reserved and should be left unprogrammed 1 3 Give WR a tWLWH_PFB wide negative pulse to execute the programming tWLWH_PFB is found in Table 17 Programming the Fuse bits...

Страница 43: ...er Min Typ Max Units VPP Programming Enable Voltage 11 5 12 5 V IPP Programming Enable Current 250 0 A tDVXH Data and Control Setup before XTAL1 High 67 0 ns tXHXL XTAL1 Pulse Width High 67 0 ns tXLDX...

Страница 44: ...XTAL1 or a crystal needs to be con nected across pins XTAL1 and XTAL2 The minimum low and high periods for the Serial Clock SCK input are defined as follows Low 1 XTAL1 clock cycle High 4 XTAL1 clock...

Страница 45: ...ogrammed will give the value P1 until the auto erase is finished and then the value P2 See Table 18 for P1 and P2 values At the time the device is ready for a new EEPROM byte the programmed value will...

Страница 46: ...0x xxxx xxxx xxxx xxxx xxxx Chip erase both Flash and EEPROM memory arrays Read Program Memory 0010 H000 0000 000a bbbb bbbb oooo oooo Read H high or low byte o from program memory at word address a b...

Страница 47: ...4 0 6 0V 0 12 0 MHz tCLCL Oscillator Period VCC 4 0 6 0V 83 3 ns tSHSL SCK Pulse Width High 4 0 tCLCL ns tSLSH SCK Pulse Width Low tCLCL ns tOVSH MOSI Setup to SCK High 1 25 tCLCL ns tSHOX MOSI Hold a...

Страница 48: ...Pins 200 0 mA DC Characteristics TA 40 C to 85 C VCC 2 7V to 6 0V unless otherwise noted Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL1 0 5 0 3 VCC 1 V VIL1 Input Low...

Страница 49: ...Although each I O port can source more than the test conditions 3 mA at VCC 5V 1 5 mA at VCC 3V under steady state conditions non transient the following must be observed 1 The sum of all IOH for all...

Страница 50: ...rive VIL1 VIH1 Table 23 External Clock Drive Symbol Parameter VCC 2 7V to 4 0V VCC 4 0V to 6 0V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 4 0 0 12 0 MHz tCLCL Clock Period 250 0 83 3 ns tCH...

Страница 51: ...erating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency o...

Страница 52: ...e Clocked by Internal Oscillator 0 1 2 3 4 5 6 7 8 9 10 2 2 5 3 3 5 4 4 5 5 5 5 6 ACTIVE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz I cc mA Vcc V T 85 C A T 25 C A T 40 C A 0 1 2 3 4 5 6 7 2 2 5 3 3 5 4 4...

Страница 53: ...2 5 3 3 5 4 4 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vcc 6V Vcc 5 5V Vcc 5V Vcc 4 5V Vcc 4V Vcc 3 6V Vcc 3 3V Vcc 3 0V Vcc 2 7V IDLE SUPPLY CURRENT vs FREQUENCY T 25 C A Frequency MHz I cc mA 0 0...

Страница 54: ...chdog Timer Disabled 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 2 2 5 3 3 5 4 4 5 5 5 5 6 T 25 C A T 85 C A IDLE SUPPLY CURRENT vs Vcc I cc mA Vcc V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 0 0 2 0 4 0 6 0...

Страница 55: ...nal RC Oscillator Frequency vs VCC 0 20 40 60 80 100 120 140 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25 C A POWER DOWN SUPPLY CURRENT vs Vcc I cc Vcc V WATCHDOG TIMER ENABLED 0 200 400 600 800 1000 1200...

Страница 56: ...og Comparator Offset Voltage vs Common Mode Voltage 0 0 2 0 4 0 6 0 8 1 1 2 2 2 5 3 3 5 4 4 5 5 5 5 6 ANALOG COMPARATOR CURRENT vs Vcc I cc mA Vcc V T 25 C A T 85 C A T 40 C A 0 2 4 6 8 10 12 14 16 18...

Страница 57: ...r Input Leakage Current 0 2 4 6 8 10 0 0 5 1 1 5 2 2 5 3 ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Common Mode Voltage V Offset Voltage mV V 2 7V cc T 85 C A T 25 C A 60 50 40 30 20 10 0...

Страница 58: ...Current vs Input Voltage Figure 52 Pull up Resistor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE V 5V cc I A OP V V OP T 85...

Страница 59: ...ource Current vs Output Voltage 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 V 5V cc I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE 0 2 4 6 8 10 12 14 16 18 20 0 0 5 1 1 5 2 2 5...

Страница 60: ...igure 56 I O Pin Source Current vs Output Voltage 0 5 10 15 20 25 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE V 2 7V cc 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I O...

Страница 61: ...57 I O Pin Input Threshold Voltage vs VCC Figure 58 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V Vcc I O PIN INPUT THRESHOLD VOLTAGE vs Vcc T 25 C A 0 0 02 0 04 0...

Страница 62: ...rved 33 TCCR0 CS02 CS01 CS00 page 21 32 TCNT0 Timer Counter0 8 Bits page 22 31 Reserved 30 Reserved 2F Reserved 2E Reserved 2D Reserved 2C Reserved 2B Reserved 2A Reserved 29 Reserved 28 Reserved 27 R...

Страница 63: ...PC PC 2 or 3 None 1 2 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 or 3 None 1 2 SBIS P b Skip if Bit in I O...

Страница 64: ...ter to T T Rr b T 1 BLD Rd b Bit Load from T to Register Rd b T None 1 SEC Set Carry C 1 C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1...

Страница 65: ...C to 70 C AT90S1200 4PI AT90S1200 4SI AT90S1200 4YI 20P3 20S 20Y Industrial 40 C to 85 C 12 4 0 6 0V AT90S1200 12PC AT90S1200 12SC AT90S1200 12YC 20P3 20S 20Y Commercial 0 C to 70 C AT90S1200 12PI AT...

Страница 66: ...NE A D e eB eC COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 5 334 A1 0 381 D 25 984 25 493 Note 2 E 7 620 8 255 E1 6 096 7 112 Note 2 B 0 356 0 559 B1 1 270 1 551 L 2 921 3 810 C 0 2...

Страница 67: ...1 27 0 050 BSC 13 00 0 5118 12 60 0 4961 0 30 0 0118 0 10 0 0040 2 65 0 1043 2 35 0 0926 0 8 1 27 0 050 0 40 0 016 0 32 0 0125 0 23 0 0091 Controlling dimension Inches 20S 20 lead Plastic Gull Wing S...

Страница 68: ...0 015 0 25 0 010 PIN 1 ID 7 33 0 289 7 07 0 278 0 21 0 008 0 05 0 002 1 99 0 078 1 73 0 068 0 20 0 008 0 09 0 004 0 95 0 037 0 63 0 025 0 8 PIN 1 20Y 20 lead Plastic Shrink Small Outline SSOP 5 3mm b...

Страница 69: ...upt Hardware Stack 8 EEPROM Data Memory 9 Instruction Execution Timing 9 I O Memory 10 Reset and Interrupt Handling 12 Sleep Modes 19 Timer Counter0 20 Timer Counter0 Prescaler 20 Watchdog Timer 23 EE...

Страница 70: ...mum Ratings 48 DC Characteristics 48 External Clock Drive Waveforms 50 External Clock Drive 50 Typical Characteristics 51 AT90S1200 Register Summary 62 Instruction Set Summary 63 Ordering Information...

Страница 71: ...Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Memory Atmel Corporate 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 436 4270 FAX 1 408 436...

Страница 72: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Atmel AT90S1200 12SC AT90S1200A 4YI AT90S1200A 4SI AT90S1200A 12PC AT90S1200A 4PC...

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