5 4
5 4
5 4
5 4
5 4
3.4.3
3.4.3
3.4.3
3.4.3
3.4.3 Chipset Configuration
Chipset Configuration
Chipset Configuration
Chipset Configuration
Chipset Configuration
Memory Remap Feature
Use this item to enable or disable memory remap feature. Configuration
options: [Enabled] and [Disabled]. The default value is [Disabled].
DRAM Frequency
If [Auto]
is selected, the motherboard will detect the memory module(s)
inserted and assigns appropriate frequency automatically. You may select
[333MHz (DDR2 667)], [400MHz (DDR2 800)] or [533MHz (DDR2 1066)] for
DDR2 memory modules, or select [533MHz (DDR3 1066)] or [667MHz (DDR3
1333)] for DDR3 memory modules. The configuration options depend on the
CPU and memory module you adopt on this motherboard. Please refer to page
9 for the CPU FSB frequency and its corresponding memory support frequency.
Flexibility Option
The default value of this option is [Disabled]. It will allow better tolerance for
memory compatibility when it is set to [Enabled].
BIOS SETUP UTILITY
v02.54 (C) Copyright 1985-2005, American Megatrends, Inc.
Chipset Settings
Memory Remap Feature
DRAM Frequency
Flexibility Option
DRAM tCL
DRAM tRAS
DRAM tWR
DRAM tWTR
DRAM tRRD
DRAM tRTP
DRAM CH0 RCOMP ODT
DRAM CH1 RCOMP ODT
DRAM CH0 tRD
DRAM CH1 tRD
DRAM tRCD
DRAM tRP
DRAM tRFC
[Auto]
[Disabled]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Disabled]
Select Screen
Select Item
+ -
Change Option
F1
General Help
F10
Save and Exit
ESC
Exit
F9
Load Defaults
ENABLE: Allow
remapping of
overlapped PCI memory
above the total
physical memory.
DISABLE: Do not allow
remapping of memory.
Advanced
Standard Memory Info : 5-5-5-15-36-5-3-3-3
Advanced Memory Info : 18-18-4-4-0-0
Intel (R) C-STATE tech.
Intel (R) C-STATE tech. is achieved by making the power and thermal control
unit part of the core logic and not part of the chipset as before. Migration of the
power and thermal management flow into the processor allows us to use a
hardware coordination mechanism in which each core can request any C-state
it wishes, thus allowing for individual core savings to be maximized. The CPU
C-state is determined and entered based on the lowest common denominator
of both cores’ requests, portraying a single CPU entity to the chipset power
management hardware and flows. Thus, software can manage each core
independently, while the actual power management adheres to the platform
and CPU shared resource restrictions. Configuration options are: [C2], [C3],
[C4] and [Disabled]. The default value is [Disabled].
