Artesyn MVME5100, Руководство программиста, Страница: 73 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
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While the PCI Slave is filling the PCI FIFO with write data, the PPC Master can be moving
previously posted write data onto the PPC60x bus. In general, the PPC60x bus is running at a
higher clock rate than the PCI bus, which means the PCI bus can transfer data at a continuous
uninterrupted burst while the PPC60x bus transfers data in distributed multiple bursts. The
PHB write posting mechanism has been tuned to create the most efficient possible data
transfer between the two busses during typical operation. It is conceivable that some
non-typical conditions could exist that would upset the default write post tuning of the PHB.
For example, if a PPC60x master is excessively using PPC60x bus bandwidth, then the additional
latency associated with obtaining ownership of the PPC60x bus might cause the PCI Slave to
stall if the PCI FIFO gets full. If the PCI Slave is continuously stalling during write posted
transactions, then further tuning might be needed. This can be accomplished by changing the
WXFT (Write Any Fifo Threshold) field within the PSATTx registers to recharacterize PHB write
posting mechanism. The FIFO threshold should be lowered to anticipate any additional
latencies incurred by the PPC Master on the PPC60x bus. Table 2-4 summarizes the PHB
available write posting options.
The PPC Master has an optional read ahead mode controlled by the RAEN bit in the PSATTx
registers that allows the PPC Master to prefetch data in bursts and store it in the PCI FIFO. The
contents of the PCI FIFO is then used to satisfy the data requirements for the remainder of the
PCI read transaction. The PHB read ahead mechanism is tuned for maximum efficiency during
typical operation conditions. If excessive latencies are encountered on the PPC60x bus, it may
be necessary to tune the read ahead mechanism to compensate for this. Additional tuning of
the read-ahead function is controlled by the RXFT/RMFT (Read Any FIFO Threshold/Read
Table 2-4 PPC Master Write Posting Options
WXFT WPEN PPC60x Start PPC60x Continuation
xx 0 FIFO = 1 dword FIFO = 1 dword
00 1 FIFO >= 4 cache lines FIFO >= 1 cache line
01 1 FIFO >= 3 cache lines FIFO >= 1 cache line
10 1 FIFO >= 2 cache lines FIFO >= 1 cache line
11 1 FIFO >= 1 cache lines FIFO >= 1 cache line