Artesyn MaxCore MC1600, Инструкция по установке и эксплуатации, Страница: 45 / 118

System Overview
MC1600 Extreme Edge Server Installation and Use (6806870A02A) 43
1.7.1.2 PCI Express Gen2
The Integrated PCH Logic additionally implements eight lanes of PCIe Gen2 that can be split
into eight root ports. The ports support Gen1 (2.5Gb/s) and Gen2 (5Gb/s) speeds. Lanes 1-4
and lanes 5-8 can independently be configured as four x1, two x2, one x2 and two x1, or one
x4 port(s).
On the Extreme Edge Server, lanes 1-4 of CPU1 and CPU2 are configured as four x1 ports. These
ports are connected according to the following table. Default routing of the second MAC/PHY
is to CPU2 on dual-CPU variants, and to CPU1 on single-CPU variants.
1.7.2 Ethernet Interface
Each CPU has one 10Gb Ethernet interface to the Ethernet switch. The CPUs also have one
10Gb Ethernet interface directly between them. In addition, CPU1 has one 1Gb Ethernet
interface to a front panel RJ-45 connector. There is a second front panel RJ-45 port that can
come from CPU1 or CPU2 as a build option. These are described in more detail below.
1.7.2.1 Gigabit Ethernet Controller
The integrated Gigabit Ethernet controller is not used on CPU1 or CPU2.
1.7.2.2 PCIe-Based Gigabit Ethernet
One Ethernet MAC/PHY is connected to CPU1 via PCIe and provides a front panel
10/100/1000Base-T port, denoted ETH1 on the front panel. The second Ethernet MAC/PHY is
connected to CPU1 or CPU2 via PCIe and also goes to a front panel 10/100/1000Base-T port,
denoted ETH2 on the front panel. By default, this port comes from CPU2 on dual-CPU variants
and from CPU1 on single-CPU variants.
Table 1-6 PCI Express Gen2 (PCH) Interfaces
CPU
PCH PCIe Port
Group
Port (Lane) Destination Link Speed
CPU1 Lanes 1-4 1 Ethernet Switch 5.0Gbps (Gen2)
CPU1 Lanes 1-4 2 Ethernet MAC/PHY A 2.5Gbps (Gen1)
CPU1 Lanes 1-4 3 Ethernet MAC/PHY B (option) 2.5Gbps (Gen1)
CPU2 Lanes 1-4 3 Ethernet MAC/PHY B (default) 2.5Gbps (Gen1)
CPU1 Lanes 1-4 4 BMC 2.5Gbps (Gen1)