Artesyn BajaPPC-750, Руководство пользователя

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Universe Configuration Registers 6-13
0002M621-15
The PCI Slave Image 0 Control Register, LSI0_CTL, at hex offset 100
16
defines the
general VMEbus and PCI bus controls.
6.2.7 VMEbus Slave Image Registers
The Universe also allows up to eight VMEbus slave images. Each image has a con-
trol register, base address register, bound address register, and a translation offset
register. All these registers have 64-kilobytes of resolution, except for the VSI0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN PWEN Reserved VDW Reserved VAS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGM SUPER Reserved VCT Reserved LAS
Register Map 6-5. Universe PCI Slave Image 0 Control, LSI0_CTL
EN Enable the image. (power-up option, disable when configuring).
Binary 0=disabled, 1=enabled.
PWEN Posted write enable.
Binary 0=disabled, 1=enabled.
VDW Maximum data width for VMEbus.
Binary 00=8 bits, 01=16 bits, 10=32 bits, 11=64 bits.
VAS VMEbus address space. (power-up option)
Binary 000=A16, 001=A24, 010=A32, 011=reserved, 100=reserved,
101=CR/CSR, 110=user1, 111=user2.
PGM Program/data AM code.
Binary 00=data, 01=program, all others=reserved.
SUPER Supervisor/user AM code.
Binary 00=non-privileged, 01=supervisor, all others=reserved.
VCT VMEbus cycle type.
Binary 0= single cycles only, 1=single cycles and block transfers.
LAS PCI bus memory space. (power-up option)
Binary 0=memory space, 1=I/O space.