Artesyn BajaPPC-750, Руководство пользователя

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PCI Interface 5-7
0002M621-15
5.4.2 Timing
The module interface transfers data between PCI and local memory at burst data
rates. When two modules are installed, they both contend for ownership of a
common bus, which may reduce the individual performance of each module.
Specific transfer rates to the PCI bus are dependent on the module design.
NOTE. A module may burst up to 32 long words to or from DRAM before a
boundary crossing occurs, starting a new cycle.
Many PMC modules also incorporate a bridge chip between their PCI and local
busses, essentially creating two bridges that must be crossed to complete a cycle.
Often, the second bridge is a source of long delays due to the associated bus
acquisition latency. Initialization and time-out values should be set up to accom-
modate any additional latency.
5.4.3 Interrupts
Each module has four interrupt lines which are routed through the interrupt con-
troller programmable logic device (PLD) to the CPU’s interrupt input. Refer to
Section 3.4 for details.
5.4.4 Arbitration
PCI arbitration for the BajaPPC-750 is handled by the Winbond Systems Labora-
tory W83C553 ISA Bridge chip. This is a programmable arbiter that supports
eight masters. Upon power-up in the default mode, the arbiter allows all PCI mas-
ters equal access to the local bus. However, the relative priority can be adjusted by
manipulating the PCI Priority Control Register 1 starting at index 80
16
. See the
W83C553 data book for complete details on this register.
7 6 5 4 3 2 1 0
BNK [3:1] Rotate Enable BNK4 Fixed Mode BNK [3:1] Fixed Mode
Register Map 5-3. Winbond PCI Priority Control