Counter/Timer Registers
9-3
The bits (0:7) return the current state of the timer. These status bits are modified
by the timer and can change at any time. The interrupt pending, overflow, and
count-in-progress status bits are directly controlled by the state of the timer, and
are used to determine the state of the timer.
The lowest four bits of this register return the contents of CTMR. These bits are
static in that they are only affected by reset and writing to CTMR, and are unaf-
fected by the current state of the counter/timer.
9.2.4 Interrupt Acknowledge Register
The Interrupt Acknowledge Register, CTIA, clears the interrupt and overflow bits
of CTSR. The interrupt pending and overflow status bits described above can be
cleared either by clearing the enable bit in CTMR that resets the timer, or by writ-
ing to the register that clears the status bits without affecting the timer.
CInPrg
The count-in-progress bit indicates that the timer has not reached a ter-
minal count of zero. In timer mode this bit is set when the count is
stopped. In counter mode this bit may only be cleared momentarily.
Ovflow
The overflow bit is set if the counter has reached a terminal count of zero
and an interrupt is still present. This bit is also unaffected by the state of
CTMR’s overflow enable bit.
InPend
The interrupt pending bit is set if the counter reaches a terminal count of
zero, and is unaffected by the interrupt enable bit of CTMR.
StrStp
The start/stop timer bit is initially set and cleared through CTMR, but
under several conditions can be cleared by the counter. These conditions
occur when the timer is configured as a timer and has reached the termi-
nal count, and when the timer is configured to stop on overflow and an
overflow has occurred.
IntrEn
Interrupt enable.
OvFlEn
Overflow enable.
CTMode
Counter/timer mode.
Enable
Enable.
Содержание BajaPPC-750
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