Artesyn BajaPPC-750, Руководство пользователя

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9
Counter/Timers
The interrupt control and counter/timer functions for the BajaPPC-750 are han-
dled by a programmable logic device (PLD). Interrupts from the processor, reset
facilities, Ethernet, VMEbus, PMC, and ISA subsystems are routed by this PLD. It
is addressed by four lines from the boot ROM and has 32 DRAM data lines.
NOTE. Please refer to Section 4.5 for information about the BajaPPC-750 real-
time clock.
9.1 Counter/Timers
The BajaPPC-750 has two programmable 32-bit counter/timers that provide both
continuous and one-shot interrupts. Continuous interrupts may be generated
with a period of 960 nanoseconds to approximately 4.3 minutes. Counter/timer
interrupts are managed by the interrupt controller, which drives the interrupt
input to the CPU. For details, see Section 3.4 on interrupt handling.
9.2 Counter/Timer Registers
Each timer is programmed through three read registers and three write registers.
These registers sit on data bus bits DH(0:7) and should be accessed as bytes. The
registers are listed in the table below, followed by sections briefly describing each
one.
Table 9-1. Counter/Timer Registers
Hex Address Read Function Write Function
FF9A,0050 Timer 2 Period Register (CTPR) Timer 2 Period Register (CTPR)
FF9A,0040 Timer 2 Status Register (CTSR) Timer 2 Mode Register (CTMR)
FF9A,0030 Timer 2 Count Register (CTCR) Timer 2 Interrupt Acknowledge (CTIA)
FF9A,0020 Timer 1 Period Register (CTPR) Timer 1 Period Register (CTPR)
FF9A,0010 Timer 1 Status Register (CTSR) Timer 1 Mode Register (CTMR)
FF9A,0000 Timer 1 Count Register (CTCR) Timer 1 Interrupt Acknowledge (CTIA)