Artesyn Embedded Technology ATCA-7540, Инструкция по установке и эксплуатации, Страница: 307 / 324

IPMI Feature Set
ATCA-7540 Installation and Use (6806871A01A) 307
9.5 Power-On Self-Test (POST)
POST is executed at IPMC startup when either a hard (blade physically extracted/reinserted) or
a cold (IPMI Command) reset is performed. POST verifies the functionality of SRAM, IPMB-0,
EEPROM data storage, FRU-Information, and all devices (primarily sensors) attached to the
IPMC's private master-only I²C bus. A detailed description of POST tests are as follows:

FRU-Information - Verifies that the FRU-Information is readable from the external
EEPROM where it is stored. Once read, each section's checksum is computed and
validated.

IPMB-0 - Reads the ready signals coming from the I²C buffers. If this test passes, both
ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are enabled.

EEPROM - Verifies that the EEPROM contents are readable via I²C. Since the IPMC
stores its runtime and persistent data here, proper operation is crucial.

Master-Only I²C - Verifies that all expected devices attached to the master-only I²C
bus are accessible.
To obtain results of POST, the IPMC supports the IPMI standard command Get Self Test Results
with OEM extensions. This IPMI command can be run at anytime.
9.6 Ejector Handle De-Bounce
The handle switch de-bouncing algorithm is used to configure a programmable delay. The
IPMC waits before ejector handle state changes are accepted. This is provided to avoid
accidental FRU extraction caused by service-teams during servicing other FRUs.
The ejector handle de-bounce function can be enabled, disabled, and configured with the use
of the OEM command Set/Get Feature Configuration. For details, see
Set Feature Configuration
on page 255 .