NO
NOTE!
TE!
The T3 and T4 trip relays are always latched. The BO1 binary output function is always non-
latched.
4.4.1 Scheme selection
This chapter describes the schemes that are available to this unit. The schemes are configured using
the DIP switches numbered 1…4 ("Scheme selection"). For detailed instructions on each of the
available schemes please refer to the AQ-SAS™ booklet (can be found at
). Please
note that there are four booklets: two are for schemes based on IEC standards (MV and LV versions)
and the other two for schemes based on ANSI standards (MV and LV versions).
4.4.2 Available logic schemes
The schemes described below are the most important ones for this unit. However, additional schemes
are also available; please contact your nearest Arcteq representative for more information on
those schemes.
SS:0
The logic scheme SS:0 can be applied as a stand-alone arc protection scheme, but it can also be used
for protecting non-selective outgoing feeder compartments. Depending on the purpose you can
choose between the two tripping modes to trip all the circuit breakers: the light-only mode L>, or the
light and overcurrent mode L> + I>.
You can find a more detailed description of this scheme in the AQ-SAS
TM
booklet.
Figure. 4.4.2 - 9. The logic diagram of SS:0.
A
AQ
Q-101 (A
-101 (AQ
Q-101D
-101D))
Instruction manual
Version: 2.01
18
© Arcteq Relays Ltd
IM00006
Содержание AQ 102
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