AOC LE32D5520, Руководство по обслуживанию

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53
R4035 0R05 OHM
R4021 NC 4.7K 1/16W
R4036 NC 4.7K 1/16W
R4031 NC 4.7K 1/16W
R4047 NC 4.7K 1/16W
R4017 0R05 OHM
R4002 0R05 OHM
R4030 0R05 OHM
R4046 0R05 OHM
R4014 NC 0R05 OHM
R4025 0R05 OHM
R4040 NC 0R05 OHM
R4018 NC 4.7K 1/16W
R4011 NC 0R05 OHM
R4003 NC 4.7K 1/16W
R4006 NC 4.7K 1/16W
R4020 0R05 OHM
R4043 0R05 OHM
R4026 NC 4.7K 1/16W
R4044 NC 4.7K 1/16W
R4005 0R05 OHM
3.3V
F_OE
FRA10
FRA11
F_WE
FRA15
FRA14
FRA13
FRA12
FRA6
FRA7
FRA8
FRA5
FRA0
R4001 4.7K
R4004 4.7K
R4007 4.7K
R4010 4.7K
R4013 4.7K
R4016 4.7K
R4019 4.7K
R4024 4.7K
R4029 4.7K
R4034 4.7K
R4039 4.7K
R4042 4.7K
R4045 4.7K
SX_TESTCON
C4039
10N 50V
C4037
10N 50V
C4045
10N 50V
R4121
0R05 1/10W
C4017
100N 16V
C4023
100N 16V
C4015
100N 16V
C4014
10uF 6.3V
C4001
10uF 6.3V
C4022
10N 50V
C4024
10N 50V
C4009
10N 50V
C4012
10uF 6.3V
C4002
10uF 6.3V
C4010
10uF 6.3V
C4038
10N 50V
C4006
100N 16V
C4035
10N 50V
C4011
10uF 6.3V
C4004
100N 16V
C4003
100N 16V
C4043
10N 50V
C4005
100N 16V
C4013
10uF 6.3V
C4008
10uF 6.3V
C4018
100N 16V
C4042
10N 50V
C4040
10N 50V
C4044
10N 50V
C4021
10N 50V
C4036
10N 50V
C4041
10N 50V
C4019
100N 16V
C4016
100N 16V
C4007
100N 16V
1
0 0
C4020
10N 50V
Normal Mode
1 1
1
0
TESTMOD TESTCON
3VSB
HP_VCC_15
3.3V
R4033 NC 4.7K 1/16W R4032 0R05 OHM
Simulation Mode(ATE)
Scan Mode
EJTAG Mode
Work Mode
0
HP_VCC_15
3VSB HP_VCC1V
3.3V
FRA12
7
EJTAG Mode Selection
MIPS Boot ROM width selection
5 Internal 8051 bus Master/Slave selection
3
1 0 : 8bit 1 : 16bit(*)
2
Description & Setting(* as default setting)
F_WE
F_OE
FRA15
FRA13
R4009 NC 4.7K 1/16W
4
Boot from SPI or Parallel Flash
FRA14 0 : Slave 8051 1 : Master 8051 (*)
OneNand Flash sync mode clock enable
No Configure Pin
FRA11
0 : ASYNC mode 1 : SYNC mode(*)
Internal E2PROM or EFUSS burning mode selection
6
(Option 1 only used in Chip production)
0 : SPI Enabled 1 : Parrallel FLASH Enabled(*)
CPU Little Endian Mode enable 0 : little endian 1 : big endian(*)
PIN
0 : non-daisy chain mode(*) 1 : daisy chain mode
1 : burn code for eeprom
0 : normal function(*)
11
Lexru Bus Master Select MASTSEL
FRA5
FRA0
12
0 : Normal(*) 1 : Internal Switch Inverted
9
STB_EN
Control Core MIPS Clock Switch
FRA_[7:6]
0 : Normal(*) 1 : Internal Switch Inverted
00 : address mapping mode 1(*)
01 : address mapping mode 2
10 : address mapping mode 3
11 : address mapping mode 4
Control CPU_CLK Clock Switch
StandBy Mode Enable
Seclet internal 8051 bus or Slave I2C for debug
0 : Disable Slave I2C/Enable 8051
1 : Enable Slave I2C/Disable 8051(*)
FRA8
8
NAND TYPE
NAND boot enable FRA10
0 : Internal 8051(*) 1 : External 8051(ATE mode)
0 : disable 1 : enable(*)
Boot from SPI (System Config NAND+SPI)
10
0 : Disable boot from Nand(*)
1 : Enable boot from Nand
R4012 4.7K
R4015 4.7K
R4041 4.7K
SX_TESTMOD
MASTSEL
STB_EN
R4022 0R05 OHM
R4037
NC 0R05 OHM
3VSB
R4023 NC 4.7K 1/16W
R4341 4.7K
R4038
4.7K
OEM MODEL Size
Rev
Date Sheet of
TPV MODEL
PCB NAME
称爹
T P V ( Top Victory Electronics Co . , Ltd. )
Key Component
絬 隔 瓜 絪 腹 F
A2
8 23 Wednesday , January 18, 2012
称爹 < >
08.SXL_3_Power_II/ Conf ig
V
DDC
D7
V
DDC
D8
V
DDC
D9
V
DDC
D1
0
V
DDC
D1
1
V
DDC
D1
7
V
DDC
D1
8
V
DDC
D1
9
V
DDC
E7
V
DDC
E8
V
DDC
E9
V
DDC
E1
0
V
DDC
E1
1
V
DDC
E1
7
V
DDC
E1
8
V
DDC
E1
6
V
DDC
F7
V
DDC
F8
V
DDC
F9
V
DDC
F1
0
V
DDC
F1
1
V
DDC
F1
6
V
DDC
F1
8
V
DDC
F1
5
V
DDC
AA1
6
VS
S
A1
VS
S
A2
6
VS
S
AF
1
VS
S
AF
26
VS
S
J1
2
VS
S
J1
3
VS
S
J1
4
VS
S
J1
5
VS
S
J1
6
VS
S
J1
7
VS
S
K1
0
VS
S
K1
1
VS
S
K1
2
VS
S
K1
3
VS
S
K1
4
VS
S
K1
5
VS
S
K1
6
VS
S
L1
0
VS
S
L1
1
VS
S
L1
2
VS
S
L1
3
VS
S
L1
4
VS
S
L1
5
VS
S
L1
6
VS
S
M9
VS
S
M1
0
VS
S
M1
1
VS
S
M1
2
VS
S
M1
3
VS
S
M1
4
VS
S
M1
5
VS
S
M1
6
VS
S
N9
VS
S
N1
0
VS
S
N1
1
VS
S
N1
2
VS
S
N1
3
VS
S
N1
4
VS
S
N1
6
VS
S
N1
7
VS
S
P9
VS
S
P1
0
VS
S
P1
1
VS
S
P1
2
VS
S
P1
3
VS
S
P1
4
VS
S
P1
5
VS
S
P1
6
VS
S
P1
7
VS
S
R9
VS
S
R1
0
VS
S
R1
1
VS
S
R1
2
VS
S
R1
3
VS
S
R1
4
VS
S
R1
5
VS
S
R1
6
VS
S
R1
7
VS
S
R1
8
VS
S
T1
0
VS
S
T1
1
VS
S
T1
2
VS
S
T1
4
VS
S
T1
5
VS
S
T1
6
VS
S
T1
7
VS
S
U9
VS
S
U1
0
V
DDC
F1
7
VS
S
U1
1
VS
S
U1
2
VS
S
U1
3
VS
S
U1
4
VS
S
U1
5
VS
S
U1
6
VS
S
U1
7
VS
S
U1
8
VS
S
V9
VS
S
V1
0
VS
S
V1
1
VS
S
V1
2
VS
S
V1
3
VS
S
V1
4
V
DDC
AA1
3
V
DDC
AA1
4
VS
S
N1
5
VS
S
T1
3
V
DDF_
S
TB
T2
4
VD
D
M
G4
VD
D
M
G5
VD
D
M
H4
VD
D
M
H5
VD
D
M
H6
VD
D
M
N5
VD
D
M
P5
VD
D
M
N6
VD
D
M
P6
VD
D
M
W4
VD
D
M
W5
VD
D
M
W6
VD
D
M
Y4
VD
D
M
Y5
VD
D
M
Y6
VD
D
M
AA4
VS
S
V1
5
V
DDC
AA1
5
V
DDF_
S
TB
AA2
0
VD
D
F
L
ASH
AB4
VD
D
F
L
ASH
AC
4
VS
S
V1
6
VD
D
F
1
D5
VD
D
F
2
AA7
VD
D
F
3
AA1
7
VD
D
F
3
AA1
8
VD
D
F
3
AB1
8
VD
D
F
3
AC
18
VD
D
F
4
F2
0
VD
D
M
AA6
VD
D
M
AA5
VD
D
M
R6
VD
D
M
R5
VD
D
M
G6
VS
S
T9
VS
S
L9
VS
S
K9
VD
D
M
J6
VDDF: for
3.3V digital IO
(3/8)
POWER/GROUND
VDDM: 1.5V, m emory I/O power VDDC: 1.0V, core power
VDDF_ST B: for
3.3V ST B IO
ASXL
27x27
U401H
R4008 0R05 OHM
C4031
100N 16V
C4026
10uF 6.3V
C4032
100N 16V
C4030
100N 16V
C4028
10uF 6.3V
C4027
10uF 6.3V
C4029
100N 16V
C4034
100N 16V
C4025
10uF 6.3V
C4033
100N 16V HP_VCC1V