AOC Envision L32W465, Руководство по обслуживанию

Страница: 40 / 91

32
’’ LCD TV Envision L32W465
40
G PIO 1
C 4 F4
2 2 p F
C 4 5 6
0 .1 u F
+
C 4 J 3
1 0 u F/1 6 V
Q 4 0 3
2 SC 2 4 1 2 K
EEPR O M_ W P 3
U AR T0 R X
FB4 1 1 3 0 0 O H M
I2 C 0 C L K
R 4 L 8
1 0 K£ [
"1110" - Boot from 8-bi t NOR Flash
C 4 K5
1 0 p F
D 5 V
I2 C 1 D ATA
TAPSEL
I2 C 1 D ATA
I2 C 1 D ATA
U AR T1 R X
R 4 6 7
1 K£ [ 1 /1 6 W
VC C 3 V3 _ G 9
¾§ÕñÆ¥Å䣬ÓÉ 10 PF
¸ÄΪ 22 PF
5/12 HR/JASON
VC C 3 V3 _ G 9
TMS
VC C 3 V3 _ G 9
C 4 F3
2 2 p F
VC C 9 A
IR R
U 4 1 9 N C / PC A9 5 5 4 D H
1
2
3
4
5
6
7
8 9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
A0
A1
A2
I/O 0
I/O 1
I/O 2
I/O 3
VSS I/O 4
I/O 5
I/O 6
I/O 7
IN T
SC L
SD A
VD D
VC C 3 V3 _ G 9
R XD _ O U T1
SIO I/F
TMS
G PIO 0 TP4 2 0
1
C 4 9 7
1 u F
G PIO 3
R 4 2 7 1 K£ [ 1 /1 6 W
R 4 3 8 4 .7 K£ [ 1 /1 6 W
TAPSEL
U AR T1 R X
I2 C 1 C L K
TR STN
C N 4 0 2
N C / 3 3 G 8 0 0 9 3
1
2
3 C 4 J 5
0 .1 u F/1 6 V
C 4 K4
1 0 p F
I2 C 1 C L K
TXD _ O U T1
C 4 9 5
1 u F
TC K
R 4 1 6 3 3 £ [ 1 /1 6 W
TD I
PU 1
R 4 H 4
4 .7 K£ [ 1 /1 6 W
TP4 0 1
1
TC K
TP4 0 2
1
TR STN
G PIO 3
TO RF SW
B
P age 06 - GP IO I/F
B
6 1 9 W e d n e s d a y , Ma y 1 7 , 2 0 0 6
7 1 5 T1 9 6 1 -
Title
Siz e D o c u me n t N u mb e r R e v
D a te : Sh e e t o f
R 4 4 0 4 .7 K£ [ 1 /1 6 W
I2 C 0 D ATA
C N 4 1 1
N C / E- J TAG 2 X7
1 2
3 4
5 6
7 8
9 1 0
1 1 1 2
1 3 1 4
R 4 H 3
4 .7 K£ [ 1 /1 6 W
U AR T1 TX
R 4 P8
1 0 K£ [ 1 /1 6 W
I2 C 0 D ATA
R 4 3 6 4 .7 K£ [ 1 /1 6 W
I2 C 0 C L K
CHIP ID:42H
VC C 3 V3 _ G 9
PU 2
R 4 3 3
4 .7 K£ [ 1 /1 6 W
D 5 V
U AR T0 TX
R 4 3 0
4 .7 K£ [ 1 /1 6 W
C 4 9 8
1 u F
2 3 2 XC VR
U 4 0 8
H IN 2 3 2
1 3
8
1 1
1 0
1
3
4
5
2
6
1 2
9
1 4
7
1 6 1 5
R 1 IN
R 2 IN
T1 IN
T2 IN
C +
C 1 -
C 2 +
C 2 -
V+
V-
R 1 O U T
R 2 O U T
T1 O U T
T2 O U T
VC C G N D
R XD _ O U T1
R 4 2 6 1 K£ [ 1 /1 6 W
VC C 3 V3 _ G 9
R 4 4 3
N C / 1 K£ [
R 4 1 3 5 .9 K£ [
IR R 1 5
TD I
R ESETN 4 ,8 ,1 5
C N 4 0 6
1
2
VC C 9 A
J TAG _ R STN 1 5
TD O
R 4 3 7 1 K£ [ 1 /1 6 W
R 4 6 6
N C / 1 K£ [
R 4 2 9 4 .7 K£ [ 1 /1 6 W
R 4 4 1 1 K£ [ 1 /1 6 W
G PIO 2
Su p er I/O
U 4 0 1 E
ZR 3 9 6 6 0 BG C G
N 1
P1
L 3
M1
M3
M2
R 1
P2
K4
K2
L 1
K3
K5
M4
N 5
L 4
F1
G 2
H 3
G 1
H 1
J 1
J 2
J 3
H 2
J 4
W 4
V5
U 6
Y4
K1
N 3
G 3
U AR T0 TX
U AR T0 R X
U AR T1 TX
U AR T1 R X
I2 C 1 C L K
I2 C 1 D AT
I2 C 0 C L K
I2 C 0 D AT
TD O
TD I
TC L K
TMS
TR STN
C L KIN
R ESETN
IR R
TPA0
TPA0 _ N
TPB0
TPB0 _ N
TPA1
TPA1 _ N
TPB1
TPB1 _ N
TPBIAS0
TPBIAS1
G PIO 0
G PIO 1
G PIO 2
G PIO 3
TAPSEL
C L KO U T
1 3 9 4 _ R SET
* Key Pin 12
R 4 L 7
4 .7 K£ [
I2 C 0 C L K
I2 C 1 D ATA 9 ,1 5
R F_ SEL
VC C 3 V3 _ G 9
PU 1
I2 C 0 C L K 2 ,1 2
I2 C 0 D ATA 2 ,1 2
TD O
I 2 C :
0 x A0 - 0 x AE
TP4 1 9
1
VC C 3 V3 _ G 9
TXD _ O U T1
C N 4 1 0
N C / 3 3 L 3 8 0 2 3
1
2
3
G PIO 0
TXD _ O U T 1 1
U AR T0 TX
R 4 4 5
N C / 1 K£ [
I2 C 1 C L K 9 ,1 5
C N 1 0 7
C O N N
1
2
3
G PIO 0
VC C 3 V3 _ G 9
G PIO 2
I2 C 1 C L K
G PIO 1
R 4 3 5 1 K£ [ 1 /1 6 W
R 4 3 9 1 K£ [ 1 /1 6 W
R 4 H 8
N C / 0 £ [ 1 /1 6 W
R 4 3 4
4 .7 K£ [ 1 /1 6 W
I2 C 0 D ATA
R F_ SEL
FB4 1 0 3 0 0 O H M
C 4 J 4
0 .1 u F
R 4 2 8 4 .7 K£ [ 1 /1 6 W
R 4 3 2
4 .7 K£ [ 1 /1 6 W
C 4 9 6
1 u F
R 4 H 7 N C / 0 £ [ 1 /1 6 W
VC C 3 V3 _ G 9
R XD _ IN 1 1
R ESETN
D 5 V
U AR T1 TX
X4 0 1
2 4 .5 7 6 MH z
U 4 1 2
2 4 L C 3 2 A
5
6 8
4
1
2
3 7
SD A
SC L VC C
G N D
N C 0
N C 1
N C 2 W P
D 5 V
D 5 V
PU 2
R 4 3 1
N C / 4 .7 K£ [
U AR T0 R X
JTAG/EJTAG