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Receiver Module
The Receiver Module consists of the items listed below (refer to Fig-
ure 3-3):
q
Quad Sampler/Down Conversion Module with integrated SRD
(step recovery diode)
q
Power Amplifier
q
A1, LO1 PCB
q
A2, LO2 PCB
The Receiver Module is based on a four channel, two stage
Sampler/Down Conversion module that converts the 40 MHz to
65 GHz signals to 2.5 MHz signals.
The first stage of the Receiver Module uses harmonic sampling to
down-convert the four 40 MHz to 65 GHz output signals from the Test
Set Module down to 89 MHz signals. Any input signals below
270 MHz are passed directly through the four harmonic samplers to
the second stage without down-conversion. The drive signal to each of
the harmonic samplers is a comb of harmonics generated by a step re-
covery diode (SRD).
The Power Amplifier provides the signal that drives the SRD. The in-
put to the Power Amplifier is the 357 to 536.5 MHz signal from the A1
First Local Oscillator (LO1) PCB. Regardless of the operating fre-
quency, the Power Amplifier is biased on at all times to insure opti-
mum thermal stability.
The second stage of the Receiver Module uses the 25.0 to 272.5 MHz
signal from the A2 Second Local Oscillator (LO2) PCB to down-convert
the 89 MHz signals into four 2.5 MHz IF signals TA, TB, RA, RB (two
test signals and two reference signals). Either the Reference A or the
Reference B IF signal is selected, as is appropriate for Forward/Re-
verse operation. The resultant three 2.5 MHz IF signals (Test A,
Test B, and Reference A/B) are output to the IF Section. A buffered
version of the Reference A/B signal is also fed to the A8 Source
Lock/Signal Separation Control PCB as the Source Lock signal.
The Receiver Module can also select the Reference A IF signal that is
output to the IF Section via the Test A switch path. This IF signal is
used during Line Reflect Line (LRL) Calibrations to ratio the Refer-
ence A and Reference B signals.
ANALOG SUBSYSTEM ASSEMBLIES
THEORY OF OPERATION
3-16
37XXXD MM
Содержание 37 D Series
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