Analog Devices UG-200, Руководство пользователя

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UG-200 Evaluation Board User Guide
Rev. 0 | Page 12 of 28
09436-019
DECOUPLING
OPTIONA
L
CLOC
K
PAT
H
CIRCUIT
CHARG
E
PUM
P
FILTER
PECL
LVDS
A
C
CR300
C323 C322
C307 C306
R308
R307
C304 C305
R303
3 2
1
P300
C302
C310
R311
C303
8 7 6 5 4 3 2 1
J300
R300
R306
R305
R304
R310
R309
R302
R301
R315
C311
C312
C309
C308
R316
R314
R313
R312
40
21
45
43
37
36
31
30
25
24
10
3
7
5
15
16 13
44
17
1
48 47
6
18
PAD
28 29 26 27 33 32 35 34 23 22 20
19
38 39
41
42
8
2
14
46 4
12 11
9
U300
C301
C300
C321 C320 C319 C318
C317 C316
C313
C315
C314
CP
SDO_USB
SDI_USB SCLK_USB
LF
BYPASS_LDO
AGND
AD9517-4BCPZ
1500PF
0.1UF 0.1UF
DNI
0.1UF 0.1UF
DNI
0.1UF
DNI
0.1UF
OPT_CLK_N
0.1UF
0.1UF
DNI
DNI
OPT_CLK_P
DNI
0.1UF 0.1UF 0.1UF 0.1UF
0.1UF 0.1UF
0.1UF
0.1UF
0.1UF
LNJ314G8TR
A
(GREEN)
1.00K
AD9517_CSB
0
249
DNI
.22UF
4.12K
5.11K
249
249
1.00K
1.00K
1.00K
1.00K
0
200
.033UF
BYPASS_LDO
LF
AVDD_3P3V
AVDD_3P3V
AVDD_3P3V
AVDD_3P3V
CLK-
CLK+
CLK-
CLK+
DNI
0.1UF
OPT_CLK_P
0.1UF
AVDD_3P3V
OPT_CLK_N
0.1UF
0
CP
0
TSW-104-08-T-D
100
100
1800PF
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
OUT7_N_OUT7B
OUT7_OUT7A
OUT6_N_OUT6B
OUT6_OUT6A
OUT5_N_OUT5B
OUT5_OUT5A
OUT4_N_OUT4B
OUT4_OUT4A
OUT3_N
OUT3
OUT2_N
OUT2
OUT1_N
OUT1
OUT0_N
OUT0
STATUS
CP LD
CPRSET REFMON
RSET
O
D
S
N
_
S
C SDIO SCLK
RESET_N SYNC_N
PD_N
CLK_N
CLK LF
BYPASS REFIN_N_REF2 REFIN_REF1 REF_SEL
PAD
VCP
VS
VS_LVPECL
Figure 19. DUT Active Clock Circuit