User Guide
UG-934
Rev. B | Page 7 of 13
EVALUATION BOARD SCHEMATICS AND ARTWORK
Figure 7. Schematic of the EVAL-SSM3582Z Block Diagram
Figure 8. Schematic of the EVAL-SSM3582Z
Section
TO S S M 3 5 8 2
TO S S M 3 5 8 2
TO S PD I F RX
EX T S U PPLY
PV D D I N PU T
ADDR1
ADDR0
SCL_ 3 5 8 2
SDA_ 3 5 8 2
FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
OUTL–
OUTL+
OUTR+
OUTR–
SSM3 5 8 2
SHEET- 2
SDA_ 3 5 8 2
OMCK_ I N
SCL_ 3 5 8 2
SDATA_ 3 5 8 2
FSYNC_ 3 5 8 2
BCLK_ 3 5 8 2
8 4 1 6 _ MCLK
ADDR0
ADDR1
I 2 S_ I 2 C
SHEET-3
PVDD
+ 3 V3
+ 1 V8
+ 5 V
+ 5 V_ EXT
+ 3 V3 _ EXT
+ 1 V8 _ EXT
POWER_SUPPLY
SHEET- 4
OUTL+
OUTL-
OUTR+
OUTR–
OUTPUTS
SHEET- 5
1
426
2-
006
C 2 6
0 .1 0 µ F
C1 9
0 . 1 0 µ F
1
2
J2 3
2 - JUMPER
1
2
J1 7
TP3 0
TP2 9
TP2 8
TP2 7
TP2 5
TP2 6
TP2 4
TP2 3
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP2 2
TP2 1
TP1
TP
1
2
TP
1
4
TP
1
8
TP1 0
1
PGND
2
PGND
3
AVDD_EN
4
SCL
5
SDA
6
FSYNC
7
SDATA
8
BCLK
9
PGND
1 0
PGND
11
BS
T
R
+
12
OUT
R
+
1
3
OUT
R
+
14
PV
D
D
15
PV
D
D
16
PV
D
D
17
PV
D
D
18
OUT
R
–
19
OUT
R
–
20
BS
T
R
–
2 1
PGND
2 2
PGND
2 3
DVDD_EN
2 4
AVDD
2 5
AGND
2 6
ADDR0
2 7
ADDR1
2 8
DVDD
2 9
PGND
3 0
PGND
31
BS
T
L
–
32
OU
T
L
–
33
OU
T
L
–
34
PV
D
D
3
5
PV
D
D
36
PV
D
D
37
PV
D
D
3
8
OU
T
L
+
39
OU
T
L
+
40
BS
T
L
+
41
EP
A
D
U5
SSM3 5 8 2
C1 4
0 .2 2 µ F
C1 6
0 .2 2 µ F
C1 3
1 0 µ F
C1 7
1 0 µ F
C2 9
1 0 µ F
C3 7
1 0 µ F
C3 1
0 .2 2 µ F
C3 3
0 .2 2 µ F
TP
3
8
TP
3
4
TP
3
2
R1
7
47
k
Ω
C1 5
0 . 1 0 µ F
C3 2
0 . 1 0 µ F
AB
1
2
3
JP
8
JU
M
P
E
R
2
S
IP
3
AB
1
2
3
JP
9
JU
M
P
E
R
2
S
IP
3
C4 3
1 0 pF
C4 4
1 0 pF
C4 5
1 0 pF
+ 1 V8
AVDD_ 3 5 8 2
DVDD_ 3 5 8 2
ADDR1
ADDR0
AVDD_ 3 5 8 2
LDO_ 1 V8 _ EN
PVDD
PVDD
PVDD
PVDD
SCL_ 3 5 8 2
GND
GND
GND
GND
GND
SCL_ 3 5 8 2
SDA_ 3 5 8 2
FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
OUT
L
–
OUT
L
+
OU
T
R
+
OU
T
R
–
+5V
AVDD_ 3 5 8 2
PV DD
AVDD_ 3 5 8 2
ADDR0
ADDR1
LDO_ 5 V_ EN
S DA_ 3 5 8 2
BCLK_ 3 5 8 2
S DATA_ 3 5 8 2
FS YNC_ 3 5 8 2
142
62
-007