Functional Description
10-14
ADSP-214xx SHARC Processor Hardware Reference
companding algorithms, A-law and
μ
-law, performed according to the
CCITT G.711 specification. The type of companding can be selected
independently for each SPORT. Companding is selected by the
DTYPE
field of the
SPCTLx
control register.
Companding is supported on the A channel only. SPORT0, 2, 4
and 6 primary channels are capable of compression, while SPORTs
1, 3, 5 and 7 primary channels are capable of expansion.
In multichannel mode, when compression and expansion is
enabled, the number of channels must be programmed via the
NCH
bit in the
SPMCTLx
registers before writing to the transmit buffer.
The
SPxCSn
and
SPxCCsn
registers should also be written before
writing to transmit buffer.
When companding is enabled, the data in the
RXSPxA
buffers is the
right-justified, sign-extended expanded value of the eight received LSBs. A
write to
TXSPxA
compresses the 32-bit value to eight LSBs (zero-filled to
the width of the transmit word) before it is transmitted. If the 32-bit value
is greater than the 13-bit A-law or 14-bit
μ
-law maximum, it is automati-
cally compressed to the maximum value.
Transmit Path
If the serial port is configured as a serial transmitter, the data transmitted
is written to the
TXSPxA
/
TXSPxB
buffer. The data is (optionally) com-
panded in hardware on the primary A channel (SPORT 0, 2, 4 and 6
only), then automatically transferred to the transmit shift register, because
companding is not supported on the secondary B channels. The data in
the shift register is then shifted out via the SPORT's
SPORTx_DA
or
SPORTx_DB
signal, synchronous to the
SPORTx_CLK
clock. If framing signals
are used, the
SPORTx_FS
signal indicates the start of the serial word
transmission.
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Содержание SHARC ADSP-214 Series
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Страница 72: ...Notation Conventions lxxii ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 130: ...Programming Model 2 52 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 264: ...Programming Models 3 134 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 396: ...Effect Latency 7 28 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 520: ...Programming Model 10 62 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 616: ...Debug Features 14 22 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 1132: ...Register Listing A 306 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 1192: ...Index I 34 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...