Analog Devices EZ-KIT Lite ADSP-BF538F, Системное руководство

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ADSP-BF538F EZ-KIT Lite Evaluation System Manual 2-3
ADSP-BF538F EZ-KIT Lite Hardware Reference
The core voltage and the core clock rate can be set on the fly by the pro-
cessor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the
real-time clock (RTC) inputs of the processor. The default boot mode for
the processor is flash boot. See
“Boot Mode Select Switch (SW3)” on
page 2-13 for information about changing the default boot mode.
External Bus Interface Unit
The external bus interface unit (EBIU) connects external memory to the
ADSP-BF538F processor. The unit includes a 16-bit wide data bus, an
address bus, and a control bus. On the EZ-KIT Lite, the EBIU connects
to the SDRAM, flash memory, and expansion interfaces.
The 64 Mbytes (32M x 16 bits) of SDRAM connect to the synchronous
memory select 0 pin (
~SMS0
). Refer to “SDRAM Interface” on page 1-8
for information about SDRAM configuration. Note that SDRAM clock is
the processor’s clock out (
CLK OUT
), which must not exceed 133 MHz.
The flash memory device connects to the asynchronous memory select sig-
nals,
~AMS3
through
~AMS0
. The device provides a total of 4 MB of
external flash memory or 1 MB of internal flash memory. The processor
can use flash memory for both booting and storing information during a
standard mode of operation. Refer to
“Flash Memory” on page 1-10 for
details.
All of the address, data, and control signals are available externally via the
expansion interface (
J1–3
). The pinout of these connectors can be found
in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1 .