UG-1183
EVAL-SSM3525Z
User Guide
Rev. 0 | Page 4 of 16
POWER SUPPLY CONFIGURATION
The binding posts, J5 (PVDD) and J4 (GND), provide the power
supply to the evaluation board. Care must be taken to connect
the dc power with the correct polarity and voltage. Reverse polarity
or overvoltage can damage the EVAL-SSM3525Z permanently.
Permissible supply voltages range from 4.5 V to 17 V; higher
voltages may damage the amplifier. In addition, use an appropriate
current rated power supply to the evaluation board. Typically, a
5 A rating supply is recommended if using 4 Ω speakers and 12 V.
The EVAL-SSM3525Z has an option to generate the 5 V (AVDD),
3.3 V, 1.8 V, and 1.2 V from the PVDD supply. These voltages
are generated using the linear regulators on the evaluation
board: U3 for 5 V, U2 for 3.3 V, U4 for 1.8 V, and U5 for 1.2 V.
The 5 V and 3.3 V regulators can be turned off using Jumper
JP11 for 5 V and Jumper JP10 for 3.3 V. The 3.3 V regulator is used
for the on-board S/PDIF digital audio receiver and I
2
C pull-up.
The 1.8 V/1.2 V must be provided as IOVDD to the
SSM3525
.
The 5 V (AVDD) can be provided externally or generated
internally by the
SSM3525
. By default, the evaluation board is set
up for generating the 5 V, 3.3 V, 1.8 V, and 1.2 V using on-board
regulators; however, only PVDD and IOVDD (1.8 V) are
supplied to the
SSM3525
, and 5 V (AVDD) is generated from
on-chip LDO. After power-up, the
SSM3525
generates the
AVDD (5 V) from the on-chip regulator. The on-chip regulator
for AVDD can be enabled in Register 0x04 via I
2
C. By default,
the on-chip regulator is disabled. Jumper J23 is open, and
Jumper J17 must be fitted.
The J17 and J23 jumpers are provided to measure the IOVDD
and AVDD currents. If using the on-board regulators as a source
for the AVDD and IOVDD, Jumper J17 and Jumper J23 must be
fitted, and the on-chip AVDD regulator must be disabled in
Register 0x04.
EDGE MODE
To reduce the radiated emissions from the
SSM3525
amplifier, an
edge rate control mode is available. Register 0x05, Bit 2 (EDGE)
controls the edge rate of the switching. To enable low electro-
magnetic interference (EMI) mode, set Bit 2 of Register 0x05 to 1.
To return to normal operation, set Bit 2 of Register 0x05 to 0.
COMPONENT SELECTION
Selecting the proper components is the key to achieving the
performance required at the cost budgeted.
Output Decoupling Capacitors
There are two output filter capacitors (C1 and C2) that work
with the L2 and L3 ferrite beads. Use small size (0603 or 0402),
multilayer ceramic capacitors of dielectric type X7R or COG
(NPO) materials. The recommended value is 220 pF.
Output Ferrites
If ferrite beads are preferred for EMI filtering at the output nodes,
Table 1 shows the recommended output ferrite beads to use to
avoid excessive noise induced by the nonlinear behavior of the
ferrite beads.
I
2
C CONECTOR FOR USBi
PVDD
GND
RESET
SOUNDWIRE INTERFACE
5V REG ENABLE/DISABLE
3.3V REG ENABLE
OUTPUT
OPTICAL COAXIAL SELECT
I
2
C SELECT
I
2
C PULL-UP SELECT
IOVDD SELECT
I
2
C DEVICE
ADDRESS SETTING
I
2
S SOUNDWIRE SELECT
SPDIF EXT I
2
S SELECT
16199-
003
Figure 3. Board Settings for I
2
C to I
2
S Mode
