UG-1308
Rev. A | Page 21 of 24
LPDAC0
PGA
ADC
RCAL1
VBIAS0
TR1
T9
PR0
NR1
SW5
DR0
EXTERNAL
R
CAL
P_NODE
CALIBRATION
CURRENT
RCAL0
SE0
N_NODE
LPTIA0_N
R
LOAD
VZERO0
VBIAS0
LPTIA0_P
LPTIA0
LPRTIA0
HSTIA
P_NODE
N_NODE
LPTIA0_P
LPTIA0_N
D7
SW13
SW12
1688
7-
12
9
ADC
INPUT
MUX
VZERO0
VZERO0
VBIAS0
Figure 37. High Speed TIA, Low Power TIA0, and Switch Matrix Settings for LPRTIA0 Resistor Calibration
LPDAC1
PGA
ADC
RCAL1
VBIAS1
TR1
T9
PR0
NR1
SW5
DR0
EXTERNAL
R
CAL
P_NODE
CALIBRATION
CURRENT
RCAL0
SE1
N_NODE
LPTIA1_N
LPRTIA1
R
LOAD
VZERO1
VBIAS1
LPTIA1_P
LPTIA1
HSTIA
P_NODE
N_NODE
LPTIA1_P
LPTIA1_N
D8
SW13
SW12
1688
7-
13
0
ADC
INPUT
MUX
VZERO1
VZERO1
VBIAS1
Figure 38. High Speed TIA, Low Power TIA0, and Switch Matrix Settings for LPRTIA1 Resistor Calibration