UG-835
EVAL-ADG5248FEBZ User Guide
Rev. A | Page 6 of 14
JUMPER SETTINGS
SWITCHES AND 0 Ω RESISTORS
The switches on the evaluation board control the
ADG5248F
manually and 0 Ω resistors configure the VL supply voltage, the
voltage present on POSFV and NEGFV, and isolate the LEDs
from the rest of the system. Table 2 shows a summary of the
uses of the switches and 0 Ω resistors on the evaluation board.
Use SW2 to SW4 to control the switches of the
ADG5248F
.
Position L is tied to GND and sets the logic low. Position H is
tied to VL and sets the logic high.
Use SW1 to enable or disable the device. Position DIS is tied to
GND and disables the device, and position EN is tied to VL and
enables the device.
Table 1.
ADG5248F
Truth Table
SW4 (A2) SW3 (A1) SW2 (A0) SW1 (EN)
Connected Sx
X
1
X
1
X
1
DIS (disable) All switches off
L (low)
L (low)
L (low)
EN (enable)
S1
L (low)
L (low)
H (high)
EN (enable)
S2
L (low)
H (high)
L (low)
EN (enable)
S3
L (low)
H (high)
H (high)
EN (enable)
S4
H (high)
L (low)
L (low)
EN (enable)
S5
H (high)
L (low)
H (high)
EN (enable)
S6
H (high)
H (high)
L (low)
EN (enable)
S7
H (high)
H (high)
H (high)
EN (enable)
S8
1
X = don’t care.
R18 connects the on-board LDO regulator to the VDD supply.
Remove this header to isolate the LDO regulator from the input
screw terminal. Change the 0 Ω resistor from the R20 position
to the R21 position to use an alternative digital supply voltage
from the EXT_VL screw terminal.
Resistors R14, R36, R47, and R48 connect the LEDs to the digital
power supply. R37 and R50 connect the FF and SF pins of the
ADG5248F
to the LED controls.
Resistors R34, R39, and R41 configure POSFV to either the
voltage present on POSFV on J4, VDD, or VL. Resistors R35,
R40, and R42 configure NEGFV to either VSS, the voltage
present on NEGFV on J4, or GND.
SMB CONNECTORS
The SW1 to SW4 switches allow the user to manually control the
parallel interface of the
ADG5248F
. Alternatively, the SMB
connectors (EN/F2, A0/F0, A1/F1, and A2) can allow control via
the external control signals. To use the SMB connectors, remove
the 0 Ω resistors, R54 to R57. The FF/SF SMB connectors access
the FF/SF digital outputs from the
ADG5248F
.
Table 2. Switch and 0 Ω Resistor Descriptions
Label
Position
Description
SW1
EN (enable)
Logic 0 on EN/F2 pin
DIS (disable)
Logic 1 on EN/F2 pin
SW2
L (low)
Logic 0 on A0/F0 pin
H (high)
Logic 1 on A0/F0 pin
SW3
L (low)
Logic 0 on A1/F1 pin
H (high)
Logic 1 on A1/F1 pin
SW4
L (low)
Logic 0 on A2 pin
H (high)
Logic 1 on A2 pin
R35, R40, and R42
R35
NEGFV set to VSS
R40
NEGFV set to voltage on the J4 NEGFV screw terminal
R42
NEGFV set to GND
R34, R39, and R41
R34
POSFV set to voltage on the J4 POSFV screw terminal
R39
POSFV set to VDD
R41
POSFV set to VL
R20 and R21
R20
On-board LDO regulator digital voltage
R21
EXT_VL digital voltage
R18
Inserted
LDO regulator powered up
Removed
LDO regulator unpowered
R37 and R50
Inserted
FF and SF pins connected to LED
Removed
FF and SF pins disconnected from LED
R14, R36, R47, and R48
Inserted
LED connected to digital supply
Removed
LED isolated
